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A communication system employing an optical beam 16 suitable for transmission of data between a first terminal 12 and a second terminal 22. The apparatus aligns beam 16 from terminal 22 with a beam receptor 92 located in terminal 12 within a first uncertainty region TU which enables tracking of data

A communication system employing an optical beam 16 suitable for transmission of data between a first terminal 12 and a second terminal 22. The apparatus aligns beam 16 from terminal 22 with a beam receptor 92 located in terminal 12 within a first uncertainty region TU which enables tracking of data with beam 16. Optics 50 enables receipt of beam 16 and transmission of the beam along a path 58. A positioning mechanism 150 points the optics 50 to the location of the terminal 22 within a second uncertainty region TU. An acquisition sensor 96 receives at least a portion of beam 16 and locates the terminal 22 within a third uncertainty region, such as the region represented by detector quadrant AQ1, which is larger than region TU but smaller than region RU1. A controller 200 responsive to locating of terminal 22 causes positioning mechanism 150 to move at least a portion of optics 50 to successively adjust the position of the beam path relative to acquisition sensor 96. As a result, the size of the third uncertainty region TU to facilitate the commencement of tracking of beam 16.

대표청구항 ▼

A communication system employing an optical beam 16 suitable for transmission of data between a first terminal 12 and a second terminal 22. The apparatus aligns beam 16 from terminal 22 with a beam receptor 92 located in terminal 12 within a first uncertainty region TU which enables tracking of data

A communication system employing an optical beam 16 suitable for transmission of data between a first terminal 12 and a second terminal 22. The apparatus aligns beam 16 from terminal 22 with a beam receptor 92 located in terminal 12 within a first uncertainty region TU which enables tracking of data with beam 16. Optics 50 enables receipt of beam 16 and transmission of the beam along a path 58. A positioning mechanism 150 points the optics 50 to the location of the terminal 22 within a second uncertainty region TU. An acquisition sensor 96 receives at least a portion of beam 16 and locates the terminal 22 within a third uncertainty region, such as the region represented by detector quadrant AQ1, which is larger than region TU but smaller than region RU1. A controller 200 responsive to locating of terminal 22 causes positioning mechanism 150 to move at least a portion of optics 50 to successively adjust the position of the beam path relative to acquisition sensor 96. As a result, the size of the third uncertainty region TU to facilitate the commencement of tracking of beam 16. d origin O to a middle position SMof the geostationary orbit; turning the antenna through the angle α about an axis D perpendicular to a plane containing the focal line and the origin O of the focal axis; and adjusting a roll angle by turning the antenna about an axis connecting said origin O to a satellite situated at said one of the extreme positions, so as to aim at the other of said extreme positions and bring the focal line into alignment with the set of satellites situated between the extreme positions S1and S2. 2. The method according to claim 1, further comprising adjusting the azimuth angle and the elevation angle of said antenna, corresponding to said one of the extreme positions. 3. The method according to claim 2, wherein said method is used for pointing a fixed antenna having as many sources as there are target orbital positions. 4. The method according to claim 3, further comprising adjusting a height of each of said sources in a plane perpendicular to the plane containing the focal line and the origin O of the focal axis of the reflector independently of the others. 5. The method according to claim 2, wherein said method is used for pointing a fixed antenna having a single source with a steerable radiation pattern. 6. The method according to claim 2, wherein said method is used for pointing a fixed antenna having a single source which is motor-driven along the focal line. 7. A device for pointing an antenna having a reflector fixed on a support and including at least one transceiver source suitable for aiming at a plurality of satellites situated between two extreme positions S1and S2on a geostationary orbit, the device comprising a mechanism for fixing the antenna to said support, said mechanism comprising means for adjusting the position of the antenna about an azimuth axis, means for adjusting the position of the antenna about an elevation axis, and means for adjusting the position of the antenna about an axis D perpendicular to a plane containing a focal line of the antenna and an origin O of a focal axis of the reflector so as to steer the reflector transversely. 8. The device according to claim 7, wherein the antenna has as many transceiver sources as there are target orbital positions. 9. The device according to claim 7, wherein the antenna has a single transceiver source with a steerable radiation pattern. 10. The device according to claim 7, wherein the antenna has a single source that is motor-driven along the focal line. 11. The device according to claim 7, wherein the mechanism comprises a U-shaped first part co-operating with a second part fixed at one end to the support while a second end is mounted to move between side limbs of said U-shaped first part so as to enable the elevation angle of the antenna to be adjusted. 12. The device according to claim 11, wherein said first part also co-operates with a third part having a face perpendicular to the focal axis of the reflector with slots formed therein slidably receiving studs secured to the U-shaped part so as to enable the roll angle of said antenna to be adjusted. 13. The device according to claim 12, wherein the face includes a top bracket and a bottom bracket each pierced by the axis D so as to enable the angle α to be adjusted. 14. The device according to claim 13, wherein at least one of said brackets includes a slot slidably receiving an arm for enabling the antenna to be turned about the axis D and enabling its transverse direction to be held. 15. A device for pointing an array antenna with azimuth scanning fixed on a support and including an array having a plurality of radiating elements suitable for aiming at a plurality of satellites situated between two extreme positions S1and S2on a geostationary orbit, the device comprising a mechanism for fixing the antenna to said support and comprising means for adjusting the position of the array antenna about an az imuth axis, means for adjusting the position of the array antenna about an elevation axis, and means for adjusting the position of the array antenna about an axis D perpendicular to an azimuth scanning plane of the array so as to steer the array antenna transversely, said axis D being distinct from said azimuth axis. ; US-4943943, 19900700, Hayashi et al., 365/185; US-4954730, 19900900, Yoh, 307/451; US-5018104, 19910500, Urai, 365/200; US-5251169, 19931000, Josephson, 365/072; US-5420817, 19950500, Kitagawa et al., 365/226; US-5457653, 19951000, Lipp, 365/185.18; US-5541529, 19960700, Mashiko et al., 326/039; US-5818087, 19981000, Yee, 257/355; US-5818758, 19981000, Wojciechowski, 365/185.18; US-5835414, 19981100, Hung et al., 365/185.25 voltage line (V+); a first current mirror (128) connected to said first common voltage line (V+); a second common voltage line (V-); a second current mirror (126) connected to said second common voltage line (V-); a first transistor (104) having a base connected to said input line (IN), a collector connected to said first common voltage line (V+), and an emitter connected to said second common voltage line (V-) via a current sink (114); a second transistor (116) having a base connected to said input line (IN), a collector connected to said second common voltage line (V-), and an emitter connected to said first common voltage line (V+) via a current sink (120); a third transistor (124) having a base connected to said emitter of said second transistor (116), a collector connected to an input of said first current mirror (128) and an emitter forming a first node (n10); a fourth transistor (126) having a base connected to said emitter of said first transistor (104), a collector connected to an input of said second current mirror (136), and an emitter connected to the first node (n10); a fifth transistor (538) having a base connected to said emitter of said second transistor (116), a collector connected to said collector of said third transistor (124), an emitter connected to a second node (n40), said second node (n40) having an associated charge storage device (548); a sixth transistor (540) having a base connected to said emitter of said first transistor (104), a collector connected to said collector of said fourth transistor (126), and an emitter connected to said second node (n40); a first diode (240) having a first terminal connected to an output (Cm+) of said first current mirror (128) and having a second terminal; a second diode (242) having a first terminal connected to the second terminal of the first diode (240) and a second terminal connected to an output (Cm-) of said second current mirror (136); a seventh transistor (158) having a base connected to the first terminal of the first diode, a collector connected to said first common voltage line (V+), and an emitter connected to an output; and an eighth transistor (160) having a base connected to the second terminal of the second diode (242), a collector connected to said second common voltage line (V+), and an emitter connected to said output. 2. The current feedback amplifier of claim 1 wherein: said first diode (240) is biased to cut off when current delivered from said first current mirror (128) reaches a first predetermined level. 3. The current feedback amplifier of claim 1 wherein: said second diode (242) is biased to cut off when current delivered from said second current mirror (136) reaches a second predetermined level. 4. The current feedback amplifier of claim 1 wherein properties of said first and said second diodes (240,242) are selected such that only one of the first current mirror and the second current mirror will provide current to the output at a given time. 5. A current feedback amplifier comprising: a first current mirror (128) having an input and an output (Cm+); a second current mirror (136) having an input and an output (Cm-) a first pair of emitter follower transistors (124,126) with collectors connected between the inputs of the first and second current mirrors (128, 136) a second pair of emitter follower transistors (538,540) with collectors connected between the inputs of the first and second current mirrors (128, 136), and bases connected in common with corresponding transistors in the first pair of emitter follower transistors (124,126) to an input of the current feedback amplifier; a capacitor (548) connected to emitters of the first pair of emitter follower transistors; diodes (240,242) connecting the outputs (Cm+) and (Cm-) of the first and second current mirrors (128, 136) a third pair of emitter follower transistors (158,160) having bases connected to respective ones of the outputs (Cm+, Cm-) of the fir st and second current mirrors (128, 136), emitters forming the output of the current feedback amplifier, and collectors connected between first and second power supply terminals (V+,V-). 6. The current feedback amplifier of claim 5, further comprising: first and second input transistors (104,116) having bases connected in common forming an input of the current feedback amplifier, a collector of the first input transistor (104) being connected to the first power supply terminal (V+), and a collector of the second input transistor (116) being connected to the second power supply terminal (V-) a first current sink (114) having a first terminal connected to the emitter of the first input transistor (104), and having a second terminal connected to the second power supply terminal (V-); and a second current sink (120) having a first terminal connected to the emitter of the second input transistor (116), and having a second terminal connected to the first power supply terminal (V+), wherein first terminals of the second current sink (120) and the first current sink (114) connected to bases of respective ones of the second pair of emitter follower transistors (538,540). 7. The current feedback amplifier of claim 6, further comprising: a feedback resistor (172) connecting the common emitters of the third pair of emitter follower transistors (158,160) to the common emitters of the first pair of emitter follower transistors (124,126). 8. A method of generating a reduced distortion amplified signal comprising the steps of: receiving a varying input signal having a first portion with values greater than zero and a second portion having values less than zero; drawing current through a first signal generation device to generate a first amplified signal based on said first portion of said varying input signal; storing current in a charge storage device in response to said first portion of said varying input signal; delivering said stored current to activate a second signal generation device when said first portion of said varying input signal reaches a first predetermined value; terminating delivery of said stored current to said second signal generation device when said varying input signal has a value less than zero; and drawing current through said second signal generation device to generate a second amplified signal based on said second portion of said varying input signal. 9. The method of generating a reduced distortion amplified signal of claim 8 further comprising the steps of: storing current in said charge storage device in response to said second portion of said varying input signal; delivering said stored current to activate said first signal generation device when said second portion of said varying input signal reaches a second predetermined value; and terminating delivery of said stored current to said first signal generation device when said varying input signal has a value greater than zero. 10. The method of generating a reduced distortion amplified signal of claim 9 wherein: said first signal generation device is a first current mirror; and said second signal generation device is a second current mirror. 11. The method of generating a reduced distortion amplified signal of claim 9 wherein said charge storage device is a capacitor. 12. The method of generating a reduced distortion amplified signal of claim 8 wherein said first predetermined level is a maximum positive value of said input signal. 13. The method of generating a reduced distortion amplified signal of claim 8, wherein said second predetermined level is a maximum negative value of said input signal. arator that produces a low voltage output by pulling the output to common when an input signal exceeds a reference voltage and that produces a floating output by not conducting when the input signal does not exceed the reference voltage. A low output from the comparator generates a base current sufficient to drive a PNP transistor, which in turn drives current to a DC output capacitor. Until the input signal exceeds the reference voltage, neither the comparator nor the PNP transistor need to conduct and, consequently, the peak detector consumes relatively little power. The peak detector can be beneficially employed in a network interface unit or other transmission line unit. which step c includes forming the single grounding member free-of discontinuous portions. 12. A non-reciprocal circuit element comprising: a circuit having at least a ferrite, transmission lines and a capacitor; input and output terminals for transferring an external signal, respectively, to and from the transmission lines; a single grounding member having shaped end portions, the shaped end portions providing ground terminals for external connection; one end of the capacitor disposed directly on a surface of the grounding member; at least one of the shaped end portions disposed between the input and output terminals at one end of the circuit, and the remaining shaped portions are disposed at an opposing end of the circuit, free of any input or output terminals. 13. The non-reciprocal circuit element of claim 12 wherein the at least one shaped end portion is disposed at one end of the grounding member and all remaining shaped end portions are disposed at an opposing end of the grounding member. 14. A non-reciprocal circuit element comprising: a circuit having at least a ferrite, transmission lines and a discrete capacitor; input and output terminals for transferring an external signal, respectively, to and from the transmission lines; a single grounding member having shaped end portions, the shaped end portions providing ground terminals for external connection; one end of the discrete capacitor disposed directly on a surface of the grounding member; and at least one of the shaped end portions disposed between the input and output terminals. nductor-forming openings with inner conductors therein, or stripline-type conductors, both of said conductors having both ends open-circuited, and said conductors being capacitively coupled together. Terminal electrodes coupled to the vicinities of two open-circuited ends of one of the resonators are used as balanced terminals on one side, and terminal electrodes coupled to the vicinities of the two open-circuited ends of the other one of the resonators are used as balanced terminals on the other side. tput, a first input coupled to a reference voltage, and a second input coupled to an output of the third comparator; a third AND gate having an output, a first input coupled to the reference voltage, and a second input coupled to an output of the fourth comparator; a fourth AND gate having an output, a first input coupled to an output of the first comparator, and a second input coupled to an output of the fifth comparator; a first OR gate having an output, a first input coupled to the output of the first AND gate, and a second input coupled to the output of the second AND gate; a second OR gate having an output, a first input coupled to the output of the third AND gate, and a second input coupled to the output of the fourth AND gate; and a NOR gate having an output, a first input coupled to the output of the first OR gate, and a second input coupled to the output of the second OR gate. 6. The receiver circuit of claim 5, further comprising: a first delay circuit coupled between the output of the first OR gate and the first input of the NOR gate; and a second delay circuit coupled between the output of the second OR gate and the second input of the NOR gate. 7. The receiver circuit of claim 6, wherein the signal select circuit comprises: a first comparator having an output, a first input coupled to the first conductor via a high pass filter and having a second input connected to a reference voltage; a second comparator having an output, a first input coupled to the second conductor via a high pass filter and having a second input connected to the reference voltage; a first inverter coupled to the output of the first comparator; a second inverter coupled to the output of the second comparator; a first AND gate having an output, a first input coupled to an output of the first inverter, and a second input coupled to an output of the second inverter; a second AND gate having an output, a first input coupled to the output of the first inverter, and a second input coupled to the output of the second OR gate; a third AND gate 86 having an output, a first input coupled to the output of the first AND gate of the signal select circuit, and a second input coupled to an output of the NOR gate; a fourth AND gate having an output, a first input coupled to the output of the second inverter, and a second input coupled to the output of the first OR gate; and an output OR gate having an output, a first input coupled to the output of the second AND gate of the signal select circuit, a second input coupled to the output of the third AND gate of the signal select circuit, and a third input coupled to the output of the fourth AND gate of the signal select circuit. 8. The receiver circuit of claim 1, wherein the signal select circuit comprises: a first comparator having an output, a first input coupled to the high signal conductor via a high pass filter and having a second input connected to a reference voltage; a second comparator having an output, a first input coupled to the low signal conductor via a high pass filter and having a second input connected to the reference voltage; a first inverter coupled to the output of the first comparator; a second inverter coupled to the output of the second comparator; a first AND gate having an output, a first input coupled to an output of the first inverter, and a second input coupled to an output of the second inverter; a second AND gate having an output, a first input coupled to the output of the first inverter, and a second input coupled to an output of the comparing circuit; a third AND gate 86 having an output, a first input coupled to the output of the first AND gate, and a second input coupled to an output of the comparing circuit; a fourth AND gate having an output, a first input coupled to the output of the second inverter, and a second input coupled to an output of the comparing circuit; and an OR gate having an output, a first input coupled to the output of the second AND gate, a second input coupled to the output of the third AND gate, and a third input coupled to the output of the fourth AND gate. 9. The receiver circuit of claim 1, wherein the fault detection circuit comprises: a first summing unit having an output, having a first input coupled to the first signal conductor, and having a second input connected to a negative reference voltage; a second summing unit having an output, having a first input coupled to the second signal conductor and having a second input connected to a positive reference voltage; a first difference unit having an output, having a plus input coupled to the output of the first summing unit and having a minus input coupled to the output of the second summing unit; a second difference unit having an output, having a minus input coupled to the output of the first summing unit and having a plus input coupled to the output of the second summing unit. 10. The receiver circuit of claim 9, wherein the fault detection circuit further comprises: a peak detector coupled between the output of the first difference unit and the comparing circuit. 11. The receiver circuit of claim 1, wherein the comparing circuit comprises: a plurality of comparators, the comparators comparing the difference signal, the first signal and the second signal to predetermined reference signals, the plurality of logic units being coupled to outputs of the comparators. 12. A receiver circuit for connecting to a differential serial bus, the bus having a high signal conductor and a low signal conductor, the receiver circuit comprising: a fault detection circuit generating a difference signal representing a difference between the high signal and the low signal; a comparing circuit having a plurality of comparators, the comparing circuit comparing the difference signal, the high signal and the low signal to predetermined voltage levels; and a signal select circuit having a first input coupled to the high signal conductor, having a second input coupled to the low signal conductor having a signal output, and having a plurality of gates coupled between the first and second inputs and the signal output, the gates also being coupled to the comparing circuit, the signal select circuit and the comparing circuit cooperating to communicate a differential signal from the bus to the signal output when no faults occur, to communicate only the high signal to the signal output when a fault is associated with the low signal, to communicate only the low signal to the signal output when a fault is associated with the high signal, and to communicate a fault signal to the signal output when faults are associated with both the low and high signal. 13. A receiver circuit for connecting to a differential serial bus, the bus having first and second signal conductors, the receiver circuit comprising: a first circuit generating a first signal representing a signal on the first conductor, a second signal representing a signal on the second conductor, and generating a difference signal representing a difference between a first signal and the second signal; a second circuit generating fault output signals as a function of the difference signal, the first signal and the second signal; and a third circuit coupled to the second circuit and coupled to the first and second conductors, the third circuit controlling communication of the first and second conductors to a signal output as a function of fault output signals. 14. A method of detecting faults on a differential serial bus, the bus having first and second signal conductors, the method comprising: generating a difference signal representing a difference between a first signal on the first conductor and a second signal on the second conductor; comparing the difference signal, the first signal and the second signal to predetermined reference signals; and controlling communication of the first and second signals as a function of results of the comparing step. 15. The method of claim 14, further comprising: detecting a peak value of the difference signal; comparing the peak value to a reference level; and controlling communication of the first and second signals also as a function of results of comparing the peak value to a reference level. 16. The method of claim 14, further comprising: comparing the difference signal with a first reference voltage; comparing the first signal with a second reference voltage; comparing the first signal with a third reference voltage; comparing the second signal with the third reference voltage; comparing the second signal with the second reference voltage; and comparing the difference signal with the first reference voltage. 17. The method of claim 16, further comprising: performing a first AND operation on a result of comparing the first signal with the second reference voltage and on a result of comparing the difference signal with the first reference voltage; performing a second AND operation on a reference voltage and on a result of comparing the first signal with the third reference voltage performing a third AND operation on the reference voltage and on a result of comparing the second signal with the third reference voltage performing a fourth AND operation on a result of comparing the difference signal with the first reference voltage and on a result of comparing the second signal with the second reference voltage; performing a first OR operation on a result of the first AND operation and on a result of the second AND operation; performing a second OR operation on a result of the third AND operation and on a result of the fourth AND operation; and performing a NOR operation on a result of the first OR operation and on a result of the second OR operation. 18. The method of claim 17, further comprising: performing a first delay operation between the first OR operation and the NOR operation; and performing a second delay operation between the second OR operation and the NOR operation. 19. The method of claim 18, further comprising: filtering the first signal with a high pass filter; comparing the filtered first signal with a reference voltage; filtering the second signal with a high pass filter; comparing the filtered second signal with the reference voltage; performing a first inverting operation upon a result of comparing the filtered first signal with the reference voltage; performing second inverting operation upon a result of comparing the filtered second signal with the reference voltage; performing a fifth AND operation 82 on results of the first and second inverting operations; performing a sixth AND operation on a result of the first inverting operation, and on a result of the second OR operation; performing a seventh AND operation 86 on a result of the fifth AND operation and on a result of the NOR operation; performing an eighth AND operation 88 on a result of the second inverting operation and on a result of the second OR operation; and performing an output OR operation on a result of the sixth, seventh and eighth AND operations. ator comprising a first phase shifting circuit and a second phase shifting circuit, each of said phase shifting circuits having an input and an output and wherein the output of said first phase shifting circuit is coupled to the input of said second phase shifting circuit and the output of said second phase shifting circuit is cross-coupled to the input of said first phase shifting circuit. 3. The circuit of claim 1 wherein said oscillator circuit comprises first, second, third and fourth phase shifting circuits, each of said phase shifting circuits having an input, a ring output and a high frequency output, wherein the ring output of said first phase shifting circuit is coupled to the input of said second phase shifting circuit, the ring output of said second phase shifting circuit is coupled to the input of said third phase shifting circuit, the ring output of said third phase shifting circuit is coupled to the input of said fourth phase shifting circuit, the ring output of said fourth phase shifting circuit is coupled to the input of said first phase shifting circuit and wherein the high frequency outputs of said first and third phase shifting circuits are coupled to a first pair of output nodes and wherein the high frequency outputs of said second and fourth phase shifting circuits are coupled to a second pair of output nodes. 4. A frequency multiplying circuit, said circuit comprising: (I) a first frequency multiplier comprising, (a) an input node for receiving an input signal having a first frequency; (b) an oscillator circuit coupled to said input node for producing first and second differential signals having an oscillation frequency equal to said first frequency; (c) an injection coupling circuit coupled between said input node and said oscillator circuit for injection locking said oscillation circuit such that said oscillation frequency is equal to said first frequency; and (d) first and second output nodes coupled to said oscillator for providing an output signal having a second frequency, wherein said second frequency is a multiple of said first frequency; and (II) a second frequency multiplier comprising, (a) first and second input nodes respectively coupled to said first and second output nodes; (b) an oscillator circuit coupled to said first and second input nodes for producing first and second differential signals having an oscillation frequency equal to said second frequency; (c) an injection coupling circuit coupled between said first and second input nodes and said oscillator circuit for injection locking said oscillation circuit such that said oscillation frequency is equal to said second frequency; and (d) first and second output nodes coupled to said oscillator for providing an output signal having a third frequency, wherein said third frequency is a multiple of said second frequency. 5. The circuit of claim 4 wherein said first frequency multiplier includes first, second, third and fourth phase shifting circuits, each of said phase shifting circuits having an input and an output, wherein the output of said first phase shifting circuit is coupled to the input of said second phase shifting circuit, the output of said second phase shifting circuit is coupled to the input of said third phase shifting circuit, the output of said third phase shifting circuit is coupled to the input of said fourth phase shifting circuit, the output of said fourth phase shifting circuit is cross-coupled to the input of said first phase shifting circuit and wherein the output of the first phase shifting circuit is coupled to said first input node of the second frequency multiplier and the output of the third phase shifting circuit is coupled to said second input node of the second frequency multiplier. 6. The circuit of claim 5 wherein said second frequency multiplier includes first and second phase shifting circuits, each of said phase shifting circuits of said second frequency multiplier having an input and an