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An enhanced heat dissipation device to extract heat from an integrated circuit device includes a thermally conductive core having upper and lower outer surface areas. The device further includes a first array of radially extending pin fin structures. The first array is thermally coupled to the upper

An enhanced heat dissipation device to extract heat from an integrated circuit device includes a thermally conductive core having upper and lower outer surface areas. The device further includes a first array of radially extending pin fin structures. The first array is thermally coupled to the upper surface area such that a cooling medium introduced around the core and the first array creates an omni-directional flow around the first array and the core to enhance heat dissipation from the integrated circuit device. The core including the first array and the lower surface area are of sufficient size to allow components on a motherboard to encroach onto the integrated circuit device when the heat dissipation device is mounted onto the integrated circuit device.

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An enhanced heat dissipation device to extract heat from an integrated circuit device includes a thermally conductive core having upper and lower outer surface areas. The device further includes a first array of radially extending pin fin structures. The first array is thermally coupled to the upper

An enhanced heat dissipation device to extract heat from an integrated circuit device includes a thermally conductive core having upper and lower outer surface areas. The device further includes a first array of radially extending pin fin structures. The first array is thermally coupled to the upper surface area such that a cooling medium introduced around the core and the first array creates an omni-directional flow around the first array and the core to enhance heat dissipation from the integrated circuit device. The core including the first array and the lower surface area are of sufficient size to allow components on a motherboard to encroach onto the integrated circuit device when the heat dissipation device is mounted onto the integrated circuit device. istance (R2) that is approximately equal to R1+δR2; a third resistance (R3) that is approximately equal to R1+δR1; and a fourth resistance (R4) that is approximately equal to R1+δR1+δR2. 5. The magnetic resistance element according to claim 4, wherein the predefined recording magnetic field pattern changes from 0 to -(Hc2+α) to 0 Oersted to change the combined resistance to correspond to R1, where α is greater than 0 Oersted. 6. The magnetic resistance element according to claim 4, wherein the predefined recording magnetic field pattern changes from 0 to (Hc2+α) to 0 Oersted to change the combined resistance to correspond to R2, where α is greater than 0 Oersted and less than Hs Oersted. 7. The magnetic resistance element according to claim 4, wherein the predefined recording magnetic field pattern changes from 0 to -(Hc2+α) to (Hc1+α) to 0 Oersted to change the combined resistance to correspond to R3, where α is greater than 0 Oersted and (Hc1+α) is less than Hc2 Oersted. 8. The magnetic resistance element according to claim 4, wherein the predefined recording magnetic field pattern changes from 0 to (Hc2+α) to -(Hc1+α) to 0 Oersted to change the combined resistance to correspond to R4, where α is greater than 0 Oersted and -(Hc1+α) is greater than Hc2 Oersted. 9. The magnetic resistance element according to claim 2, wherein a first magnetic resistance change (δR1) caused at the first tunnel barrier wall layers between the lower magnetic layer and the intermediate magnetic layer is less than a second magnetic resistance change (δR2) caused at the second tunnel barrier wall layer between the intermediate magnetic layer and the upper magnetic layer. 10. The magnetic resistance element according to claim 9, wherein the at least four predefined magnetic resistances includes: a first resistance (R1) that is greater than 0 ohms; a second resistance (R2) that is approximately equal to R1+δR1; a third resistance (R3) that is approximately equal to R1+δR2; and a fourth resistance (R4) that is approximately equal to R1+δR1+δR2. 11. The magnetic resistance element according to claim 10, wherein the predefined recording magnetic field pattern changes from 0 to -(Hc2+α) to 0 Oersted to change the combined resistance to correspond to R1, where α is greater than 0 Oersted. 12. The magnetic resistance element according to claim 10, wherein the predefined recording magnetic field pattern changes from 0 to -(Hc2+α) to (Hc1+α) to 0 Oersted to change the combined resistance to correspond to R2, where α is greater than 0 Oersted and (Hc1+α) is less than Hc2 Oersted. 13. The magnetic resistance element according to claim 10, wherein the predefined recording magnetic field pattern changes from 0 to (Hc2+α) to 0 Oersted to change the combined resistance to correspond to R3, where α is greater than 0 Oersted and less than Hs Oersted. 14. The magnetic resistance element according to claim 10, wherein the predefined recording magnetic field pattern changes from 0 to (Hc2+α) to -(Hc1+α) to 0 Oersted to change the combined resistance to correspond to R4, where α is greater than 0 Oersted and -(Hc1+α) is greater than -Hc2 Oersted. 15. The magnetic resistance element according to claim 1, the lower magnetic layer has a first coercive force (Hc1) and the intermediate magnet layer has a second coercive force (Hc2) that is less than the first coercive force, and the upper magnetic layer has a shift magnetic field (Hs) that is greater than the first and the second coercive forces of the lower and the intermediate magnetic layers. 16. The magnetic resistance element according to claim 15, wherein a first magnetic resistance change (δR1) caused at the first tunnel barrier wall layers between the lower magnetic layer and the intermediate magnetic layer is greater than a second magnetic resistance change (δR2) caused at the second tunnel barrier wall layer between the intermediate magnetic layer and the upper magneti