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Method of manufacturing a transistor in a semiconductor device 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/3205
  • H01L-021/4763
출원번호 US-0887511 (2001-06-25)
우선권정보 KR-0085138 (2000-12-29); KR-0085175 (2000-12-29)
발명자 / 주소
  • Cha, Tae Ho
  • Jang, Se Aug
  • Kim, Tae Kyun
  • Park, Dea Gyu
  • Yeo, In Seok
  • Park, Jin Won
출원인 / 주소
  • Hynix Semiconductor Inc.
대리인 / 주소
    Morgan, Lewis & Bockius LLP
인용정보 피인용 횟수 : 76  인용 특허 : 13

초록 ▼

There is disclosed a method of manufacturing a transistor in a semiconductor device. The present invention forms a Ta film or a TaNx film at a low temperature or forms a first TaNx film in which the composition(x) of nitrogen is 0.45＿0.55, on a gate insulating film in a NMOS region, so that the work

대표청구항 ▼

There is disclosed a method of manufacturing a transistor in a semiconductor device. The present invention forms a Ta film or a TaNx film at a low temperature or forms a first TaNx film in which the composition(x) of nitrogen is 0.45＿0.55, on a gate insulating film in a NMOS region, so that the work

이 특허에 인용된 특허 (13)

  1. Powell Don Carl, Ammonia passivation of metal gate electrodes to inhibit oxidation of metal.
    상세보기
  2. Bai Gang ; Liang Chunlin, Complementary metal gates and a process for implementation.
    상세보기
  3. Jun In-kyun,KRX ; Kim Young-pil,KRX ; Park Hyung-moo,KRX ; Kang Myeon-koo,KRX, Embedded memory logic device using self-aligned silicide and manufacturing method therefor.
    상세보기
  4. Hobbs Christopher C. ; Maiti Bikas ; Wu Wei, Method for forming a semiconductor device.
    상세보기
  5. Liang Chunlin ; Bai Gang, Method for making a complementary metal gate electrode technology.
    상세보기
  6. Liang Chunlin ; Bai Gang, Method for making a complementary metal gate electrode technology.
    상세보기
  7. Wilk Glen D. ; Summerfelt Scott R., Method of forming dual metal gate structures or CMOS devices.
    상세보기
  8. Tseng Horng-Huei,TWX, Method of forming poly gate and polycide gate with equal height.
    상세보기
  9. Park Ji-Soo,KRX ; Sohn Dong-Kyun,KRX, Method of forming polycide.
    상세보기
  10. Yamamoto Yoshiaki,JPX ; Aizawa Kazuo,JPX, Method of manufacturing semiconductor device with silicide layer without short circuit.
    상세보기
  11. Noguchi Mitsuhiro,JPX ; Oowaki Yukihito,JPX, Semiconductor device.
    상세보기
  12. Yasuda Hiroyasu,JPX, Semiconductor device and method of fabrication thereof.
    상세보기
  13. Gardner Mark I. ; Fulford H. Jim ; May Charles E. ; Hause Fred ; Kwong Dim-Lee, Semiconductor device having metal gate electrode and titanium or tantalum nitride gate dielectric barrier layer and process of fabrication thereof.
    상세보기

이 특허를 인용한 특허 (76)

  1. Wang, Chang-Gong; Shero, Eric; Wilk, Glen, ALD of metal silicate films.
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  2. Wang, Chang-Gong; Shero, Eric; Wilk, Glen, ALD of metal silicate films.
    상세보기
  3. Forbes,Leonard; Ahn,Kie Y., Atomic layer deposition of CMOS gates with variable work functions.
    상세보기
  4. Lindert, Nick; Cea, Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
    상세보기
  5. Doyle, Brian S.; Jin, Been-Yih; Kavalieros, Jack T.; Datta, Suman; Brask, Justin K.; Chau, Robert S., CMOS devices with a single work function gate electrode and method of fabrication.
    상세보기
  6. Nam, Gab-Jin; Lee, Myoung-Bum, Complementary metal-oxide-semiconductor transistor including multiple gate conductive layers and method of manufacturing the same.
    상세보기
  7. Ahn, Kie Y.; Forbes, Leonard, Conductive layers for hafnium silicon oxynitride.
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  8. Ahn, Kie Y.; Forbes, Leonard, Conductive layers for hafnium silicon oxynitride films.
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  9. Ahn, Kie Y.; Forbes, Leonard, Conductive layers for hafnium silicon oxynitride films.
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  10. Okura, Seiji; Suemori, Hidemi; Pore, Viljami J., Deposition of titanium nanolaminates for use in integrated circuit fabrication.
    상세보기
  11. Brask, Justin K.; Datta, Suman; Doczy, Mark L.; Blackwell, James M.; Metz, Matthew V.; Kavalieros, Jack T.; Chau, Robert S., Dielectric interface for group III-V semiconductor device.
    상세보기
  12. Wang, Chang-Gong; Shero, Eric, Doping with ALD technology.
    상세보기
  13. Polishchuk, Igor; Ranade, Pushkar; King, Tsu-Jae; Hu, Chenming, Dual work function CMOS gate technology based on metal interdiffusion.
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  14. Polishchuk,Igor; Ranade,Pushkar; King,Tsu Jae; Hu,Chenming, Dual work function CMOS gate technology based on metal interdiffusion.
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  15. Kim, Min Joo; Jung, Hyung Suk; Lee, Jong Ho; Han, Sungkee, Dual work function metal gate structure and related method of manufacture.
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  16. Kim, Min-Joo; Jung, Hyung-Suk; Lee, Jong-Ho; Han, Sungkee, Dual work function metal gate structure and related method of manufacture.
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  17. Radosavljevic, Marko; Datta, Suman; Doyle, Brian S.; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Majumdar, Amian; Chau, Robert S., Field effect transistor with metal source/drain regions.
    상세보기
  18. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
    상세보기
  19. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
    상세보기
  20. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
    상세보기
  21. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
    상세보기
  22. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
    상세보기
  23. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
    상세보기
  24. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
    상세보기
  25. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
    상세보기
  26. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
    상세보기
  27. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors.
    상세보기
  28. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
    상세보기
  29. Seo,Satoshi; Nakamura,Yasuo, Light emitting device and method of manufacturing the same.
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  30. Seo,Satoshi; Nakamura,Yasuo, Light emitting device and method of manufacturing the same.
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  31. Anderson, Brent A.; Nowak, Edward J.; Rankin, Jed H., Metal gate FET having reduced threshold voltage roll-off.
    상세보기
  32. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
    상세보기
  33. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
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  34. Haukka, Suvi; Huotari, Hannu, Method of depositing barrier layer for metal gates.
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  35. Huotari,Hannu; Haukka,Suvi; Tuominen,Marko, Method of forming an electrode with adjusted work function.
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  36. Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Chau, Robert S., Method of patterning a film.
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  37. Haukka, Suvi; Huotari, Hannu, Method of producing thin films.
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  38. Huotari,Hannu, Method to fabricate dual metal CMOS devices.
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  39. Chen, Fusen; Chen, Ling; Glenn, Walter Benjamin; Gopalraja, Praburam; Fu, Jianming, Methods and apparatus for forming barrier layers in high aspect ratio vias.
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  40. Chen, Fusen; Chen, Ling; Glenn, Walter Benjamin; Gopalraja, Praburam; Fu, Jianming, Methods and apparatus for forming barrier layers in high aspect ratio vias.
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  41. Chen, Fusen; Chen, Ling; Glenn, Walter Benjamin; Gopalraja, Praburam; Fu, Jianming, Methods and apparatus for forming barrier layers in high aspect ratio vias.
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  42. Pore, Viljami; Ritala, Mikko; Leskela, Markku, Methods for forming conductive titanium oxide thin films.
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  43. Pore, Viljami; Ritala, Mikko; Leskelä, Markku, Methods for forming conductive titanium oxide thin films.
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  44. Kang, Sang-Bom; Choi, Kyung-In; Lee, You-Kyoung; Park, Seong-Geon; Choi, Gil-Heyun; Lee, Jong-Myeong; Lee, Sang-Woo, Methods of producing integrated circuit devices utilizing tantalum amine derivatives.
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  45. Kang,Sang Bom; Lee,Jong Myeong; Choi,Kyung In; Choi,Gil Heyun; Lee,You Kyoung; Park,Seong Geon; Lee,Sang Woo, Methods of producing integrated circuit devices utilizing tantalum amine derivatives.
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  46. Zhu, Huilong; Xu, Qiuxia; Zhang, Yanbo; Yang, Hong, N-type MOSFET and method for manufacturing the same.
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  47. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
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  48. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
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  49. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
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  50. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
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  51. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
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  52. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
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  53. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
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  54. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
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  55. Brask, Justin K.; Dovle, Brian S.; Kavalleros, Jack; Doczy, Mark; Shah, Uday; Chau, Robert S., Nonplanar transistors with metal gate electrodes.
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