초록 ▼

A multi-threshold flip-flop circuit having an outside feedback is disclosed. The multi-threshold flip-flop circuit comprises a master latch and a slave latch. Coupled between an output of the slave latch and an input of the master latch, a switchable feedback path is utilized to retain logical value

A multi-threshold flip-flop circuit having an outside feedback is disclosed. The multi-threshold flip-flop circuit comprises a master latch and a slave latch. Coupled between an output of the slave latch and an input of the master latch, a switchable feedback path is utilized to retain logical values of the slave latch during a sleep mode of the flip-flop circuit.

대표청구항 ▼

1. A flip-flop circuit comprising: a master latch having a MTCMOS inverter coupled to a standard inverter; a slave latch; and a switchable feedback path, coupled between an output of said slave latch and an input of said master latch, for retaining logical values of said slave latch during a sl

1. A flip-flop circuit comprising: a master latch having a MTCMOS inverter coupled to a standard inverter; a slave latch; and a switchable feedback path, coupled between an output of said slave latch and an input of said master latch, for retaining logical values of said slave latch during a sleep mode of said flip-flop circuit. 2. A flip-flop circuit comprising: a master latch; a slave latch having MTCMOS inverter coupled to a standard inverter; and a switchable feedback path, coupled between an output of said slave latch and an input of said master latch, for retaining logical values of said slave latch during a sleep mode of said flip-flop circuit. 3. The flip-flop circuit of claim 1, wherein said MTCMOS inverter further includes a plurality of high-threshold active transistors and a plurality of low-threshold gating transistors. 4. The flip-flop circuit of claim 2, wherein said MTCMOS inverter further includes a plurality of high-threshold active transistors and a plurality of low-threshold gating transistors. 5. A flip-flop circuit comprising: a first switch connected to an input of said flip-flop circuit; a master latch having a forward MTCMOS inverter and a feedback standard inverter; a slave latch having a forward MTCMOS inverter and a feedback standard inverter; a second switch connected between an output of said master latch and an input of said slave latch; and a third switch connected between an output of said slave latch and said input of said master latch. 6. The flip-flop circuit of claim 5, wherein said MTCMOS inverter in said master latch further includes low-threshold active transistors and high-threshold gating transistors. 7. The flip-flop circuit of claim 5, wherein said MTCMOS inverter in said slave latch further includes low-threshold active transistors and high-threshold gating transistors. 8. The flip-flop circuit of claim 5, wherein said feedback standard inverter in said master latch further include high-threshold transistors. 9. The flip-flop circuit of claim 5, wherein said feedback standard inverter in said slave latch further include high threshold transistors. 10. The flip-flop circuit of claim 5, wherein said first switch is a low-threshold transistor. 11. The flip-flop circuit of claim 5, wherein said second switch is a low-threshold transistor. 12. The flip-flop circuit of claim 5, wherein said third switch is a high-threshold transistor.