초록 ▼

By providing appropriate TFT structures arranged in various circuits of the semiconductor device in response to the functions required by the circuits, it is made possible to improve the operating performances and the reliability of a semiconductor device, reduce power consumption as well as realizi

By providing appropriate TFT structures arranged in various circuits of the semiconductor device in response to the functions required by the circuits, it is made possible to improve the operating performances and the reliability of a semiconductor device, reduce power consumption as well as realizing reduced manufacturing cost and increase in yield by lessening the number of processing steps. An LDD region of a TFT is formed to have a concentration gradient of an impurity element for controlling conductivity which becomes higher as the distance from a drain region decreases. In order to form such an LDD region having a concentration gradient of an impurity element, the present invention uses a method in which a gate electrode having a taper portion is provided to thereby dope an ionized impurity element for controlling conductivity accelerated in the electric field so that it penetrates through the gate electrode and a gate insulating film into a semiconductor layer.

대표청구항 ▼

By providing appropriate TFT structures arranged in various circuits of the semiconductor device in response to the functions required by the circuits, it is made possible to improve the operating performances and the reliability of a semiconductor device, reduce power consumption as well as realizi

By providing appropriate TFT structures arranged in various circuits of the semiconductor device in response to the functions required by the circuits, it is made possible to improve the operating performances and the reliability of a semiconductor device, reduce power consumption as well as realizing reduced manufacturing cost and increase in yield by lessening the number of processing steps. An LDD region of a TFT is formed to have a concentration gradient of an impurity element for controlling conductivity which becomes higher as the distance from a drain region decreases. In order to form such an LDD region having a concentration gradient of an impurity element, the present invention uses a method in which a gate electrode having a taper portion is provided to thereby dope an ionized impurity element for controlling conductivity accelerated in the electric field so that it penetrates through the gate electrode and a gate insulating film into a semiconductor layer. ive layer; (d) forming above said active zone an upper cladding layer of a second conductive type; (e) forming a current confinement layer above said upper cladding layer, and obtaining a lamination of the lower cladding layer, the active layer, the upper cladding layer, and the current confinement layer; (f) removing at least one first near-edge portion of said lamination being located near at least one of two opposite end facets and having a first depth and a width approximately equal to a stripe width so as to produce at least one first space, by etching said lamination with a first mask which has an opening corresponding to said first near-edge portion; (g) concurrently removing at least one second near-edge portion of said lamination being located near said at least one of said two opposite end facets and having said stripe width and a second depth corresponding to a bottom of said active layer or a lower elevation, and a stripe portion of said lamination being located inside said at least one first space and having said stripe width and a third depth corresponding to a bottom of said current confinement layer or a lower elevation, so as to produce a second space, by etching said lamination with a second mask which has a stripe opening having a width corresponding to said stripe width and extending from one to the other of the two opposite end facets; and (h) forming a regrowth layer so as to fill said at least one first space and said second space. laim 10 further including a step of metal plating said chip package. 13. A method of constructing a chip package for an integrated circuit image sensor die comprising the steps of: attaching said image sensor die to a substrate carrier using die attach epoxy; attaching a one piece cover to said substrate carrier, said one piece cover having a first shelf for receiving an optical lens; applying ultra violet, UV, cure adhesive on said first shelf; placing an optical lens assembly on said UV cure adhesive; activating said image sensor die and adjusting the position of said optical lens to identify its focal distance to a predetermined target plane; and activating a UV light source to cure said UV cure adhesive and hold said optical lens in focus. 14. The method of claim 13 further including a sealing process to seal a filter glass to the top of said upper cover using epoxy. 15. The method of claim 13 further including a step of performing a wire bonding operation to connect input/output bond pads on said image sensor die to bond fingers on said substrate carrier prior to activating said image sensor die. 16. The method of claim 13 wherein said one piece cover is attached to said substrate carrier using epoxy. 17. The method of claim 13 further including the step of metal plating said body. 18. The method of claim 13 wherein said optical lens assembly includes a ring frame with an optical lens traversing its center, said step of placing said optical lens assembly on said UV cure adhesive including the steps of placing said ring frame directly on said UV cure adhesive and not permitting contact of said optical lens with said UV cure adhesive.