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Method of improving copper interconnects of semiconductor devices for bonding 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0332665 (1999-06-14)
발명자 / 주소
  • Akram, Salman
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    TraskBritt
인용정보 피인용 횟수 : 95  인용 특허 : 82

초록

An improved wire bond with the pond pads of semiconductor devices and the lead fingers of lead frames or an improved conductor lead of a TAB tape bond with the bond pad of a semiconductor device. More specifically, an improved wire bond wherein the bond pad on a surface of the semiconductor device c

대표청구항

An improved wire bond with the pond pads of semiconductor devices and the lead fingers of lead frames or an improved conductor lead of a TAB tape bond with the bond pad of a semiconductor device. More specifically, an improved wire bond wherein the bond pad on a surface of the semiconductor device c

이 특허에 인용된 특허 (82)

  1. Mei Sheng Zhou SG; Sangki Hong SG; Simon Chooi SG, Aluminum and copper bimetallic bond pad scheme for copper damascene interconnects.
  2. Ichikawa Matsuo,JPX, Bonding pad structures for semiconductor integrated circuits.
  3. Yamakawa Koji (Tokyo JPX) Iwase Nobuo (Kamakura JPX) Inaba Michihiko (Yokohama JPX), Bump and method of manufacturing the same.
  4. Akagawa Masatoshi (Nagano JPX), Chip sized semiconductor device.
  5. Carney Francis J. (Gilbert AZ) Carney George F. (Tempe AZ) Mitchell Douglas G. (Tempe AZ), Electrical interconnect and method for forming the same.
  6. Honn ; James J. ; Stuby ; Kenneth P., Electrical package for LSI devices and assembly process therefor.
  7. Nye ; III Henry A. (Bedford NY) Roeder Jeffrey F. (Brookfield CT) Tong Ho-Ming (Yorktown Heights NY) Totta Paul A. (Poughkeepsie NY), Electroplated solder terminal.
  8. Fillion Raymond A. (Niskayuna NY) Woinarowski Robert J. (Ballston Lake NY) Gdula Michael (Knox NY) Cole Herbert S. (Burnt Hills NY) Wildi Eric J. (Niskayuna NY) Daum Wolfgang (Schenectady NY), Embedded substrate for integrated circuit modules.
  9. Agarwala Birendra N. (Hopewell Junction NY) Datta Madhav (Yorktown Heights NY) Gegenwarth Richard E. (Poughkeepsie NY) Jahnes Christopher V. (Monsey NY) Miller Patrick M. (Poughkeepsie NY) Nye ; III , Etching processes for avoiding edge stress in semiconductor chip solder bumps.
  10. Lebby Michael S. (Apache Junction AZ) Kuo Shun-Meen (Chandler AZ), External communication link for a credit card pager.
  11. Dux John B. (Millbrook NY) Poetzinger Janet L. (Pleasant Valley NY) Prestipino Roseanne M. (Beacon NY) Siefering Kevin L. (Cary NC), Fabrication of discrete thin film wiring structures.
  12. Pasch Nicholas F. (Pacifica CA), Fabrication of substrates for multi-chip modules.
  13. Pasch Nicholas F. (Pacifica CA), Flexible preformed planar structures for interposing between a chip and a substrate.
  14. Degani Yinon, Flip chip metallization.
  15. Degani Yinon ; Gregus Jeffrey Alan, Flip chip metallization.
  16. Spangler Leland J. (1974 Traver Rd. ; Apt. No. 208 Ann Arbor MI 48105) Wise Kensall D. (3670 Charter Pl. Ann Arbor MI 48105), Fully integrated single-crystal silicon-on-insulator process, sensors and circuits.
  17. Farnworth Warren M. (Nampa ID) Akram Salman (Boise ID) Wood Alan G. (Boise ID), Hermetic chip and method of manufacture.
  18. Butt Sheldon H. (Godfrey IL), Hermetic microminiature packages.
  19. Chandra Grish (Midland MI) Michael Keith W. (Midland MI), Hermetic protection for integrated circuits.
  20. Pryor Michael J. (Woodbridge CT) Singhdeo Narendra N. (New Haven CT) Mahulikar Deepak (Meriden CT), Hermetically sealed package.
  21. Neugebauer ; deceased Constantine A. (late of Schenectady NY by Martha M. Neugebauer ; executrix) Wojnarowski Robert J. (Ballston Lake NY), Hermetically sealed packaged electronic system.
  22. Cain Earl S. (Napa County CA), Hermetically sealed semiconductor device.
  23. Volfson David (Worcester MA) Senturia Stephen D. (Boston MA), High-density, multi-level interconnects, flex circuits, and tape for tab.
  24. Tai King L. (Berkeley Heights NJ), Integrated circuit chip-and-substrate assembly.
  25. Wilson Arthur M. (Richardson TX), Integrated circuit product having a polyimide film interconnection structure.
  26. Moresco Larry L. (San Carlos CA) Love David G. (Pleasanton CA) Wang Wen-Chou V. (Cupertino CA), Interconnect capacitors.
  27. Hernandez Jorge M. (Mesa AZ) Hyslop Michael S. (Chandler AZ), Internally decoupled integrated circuit package.
  28. Herklotz Gnter (Bruchkbel DEX) Frderer Heinz (Grosskrotzenburg DEX) Frey Thomas (Hanau DEX), Lead frame for integrated circuits.
  29. Hooper Robert C. (Houston TX) Harrover Alexander J. (Missouri City TX) VanHoy Michael J. (Stafford TX) Terry Charles E. (Houston TX), Low cost method for forming elevated metal bumps on integrated circuit bodies employing an aluminum/palladium metallizat.
  30. Farnworth Warren M., Mask repattern process.
  31. Berndlmaier Erich (Wappingers Falls NY) Das Gobinda (Hopewell Junction NY) Viau Thomas L. (Milton VT), Metal bump for a thermal compression bond and method for making same.
  32. Culnane Thomas Moran (Lanesboro PA) Gaynes Michael Anthony (Vestal NY) Seto Ping Kwong (Endicott NY) Shaukatullah Hussain (Endwell NY), Method for attaching heat sinks directly to chip carrier modules using flexible-epoxy.
  33. Reele Samuel (Rochester NY) Pian Thomas R. (Rochester NY), Method for creating substrate electrodes for flip chip and other applications.
  34. Akasaki Hiroshi (Akishima JPX) Otsuka Kanji (Higashiyamato JPX) Hayashida Tetsuya (Nishitama JPX), Method for forming a silicide layer and barrier layer on a semiconductor device rear surface.
  35. Yamazaki Nobuto (Tachikawa JPX) Nishimura Akihiro (Hachioji JPX), Method for forming bump on semiconductor elements.
  36. Higgins ; III Leo M. (Austin TX), Method for forming conductive bumps on a semiconductor device.
  37. Farnworth Warren M. (Nampa ID) Akram Salman (Boise ID) Wood Alan G. (Boise ID), Method for forming contact pins for semiconductor dice and interconnects.
  38. Marrs Robert C. (Scottsdale AZ), Method for interconnection of integrated circuit chip and substrate.
  39. Bessho Yoshihiro (Higashiosaka JPX) Tomura Yoshihiro (Hirakata JPX), Method for mounting a semiconductor device on a circuit board using a conductive adhesive and a thermosetting resin, and.
  40. Nishi Toshio (Fukuoka JPX) Wada Yoshiyuki (Onojo JPX) Kadokami Eigo (Kasuga JPX) Yoshinaga Seiichi (Kasuga JPX), Method for mounting electronic devices.
  41. Wilson Arthur M. (Richardson TX), Method for producing an integrated circuit product having a polyimide film interconnection structure.
  42. Meikle Scott (Boise ID) Ward Valerie (Boise ID), Method of chimical mechanical polishing for dielectric layers.
  43. Neugebauer Constantine A. (Schenectady NY) Loughran James A. (Scotia NY), Method of fabricating gold bumps on IC\s and power chips.
  44. Carpenter Charles (Poughkeepsie NY) Fugardi Joseph F. (Wappingers Falls NY) Gregor Lawrence V. (Hopewell Junction NY) Grosewald Peter S. (Putnam Valley NY) Reeber Morton D. (Shrub Oak NY), Method of forming a solder interconnection capable of sustained high power levels between a semiconductor device and a s.
  45. Akram Salman, Method of forming conductive bumps on die for flip chip applications.
  46. Koopman Nicholas G. (Raleigh NC) Rinne Glenn A. (Cary NC) Turlik Iwona (Raleigh NC) Yung Edward K. (Carrboro NC), Method of forming differing volume solder bumps.
  47. Lochon Henri (Saintry-sur-Seine FRX) Robert Georges (La Ferte-Alais FRX), Method of forming metal contact pads and terminals on semiconductor chips.
  48. Gurtler Richard W. (Mesa AZ) Pearse Jeffrey (Chandler AZ) Wilson Syd R. (Phoenix AZ), Method of forming vias through two-sided substrate.
  49. Yamakawa Koji (Tokyo JPX) Koiwa Kaoru (Tokyo JPX) Iwase Nobuo (Kamakura JPX), Method of manufacturing semiconductor device and apparatus therefor.
  50. Lin Paul T. (Austin TX), Method of transferring solder balls onto a semiconductor device.
  51. Costrini Gregory ; Goldblatt Ronald Dean ; Heidenreich ; III John Edward ; McDevitt Thomas Leddy, Method/structure for creating aluminum wirebound pad on copper BEOL.
  52. Badehi Pierre (Nataf 66 ; Mobile Post Harei Yehuda 90804 ILX), Methods for producing integrated circuit devices.
  53. Licari James J. (Whittier CA) Smith Deborah J. (Fountain Valley CA), Microelectronic circuit substrate structure including photoimageable epoxy dielectric layers.
  54. Chun Heung S. (Seoul KRX), Multi-chip semiconductor package.
  55. Haluska Loren A. (Midland MI) Michael Keith W. (Midland MI) Tarhay Leo (Sanford MI), Multilayer ceramics from hydrogen silsesquioxane.
  56. Haluska Loren A. (Midland MI) Michael Keith W. (Midland MI) Tarhay Leo (Sanford MI), Multilayer ceramics from silicate esters.
  57. Wong Wah-Sang (Montebello CA) Gray William D. (Redondo Beach CA), Polyimide passivation of GaAs microwave monolithic integrated circuit flip-chip.
  58. Uzoh Cyprian E., Process for forming a copper-containing film.
  59. Pasch Nicholas F. (Pacifica CA), Process for interconnecting conductive substrates using an interposer having conductive plastic filled vias.
  60. Seppala Bryan R. (Apple Valley MN) Backer Todd G. (Apple Valley MN) Maier Lothar (Eden Prairie MN), Process for manufacturing a semiconductor device bump electrode using a rapid thermal anneal.
  61. Agarwala Birendra N. (Hopewell Junction NY), Process of making pad structure for solder ball limiting metallurgy having reduced edge stress.
  62. Koide Masateru (Kawasaki JPX) Kawamura Yasuo (Kawasaki JPX), Process of wirebond pad repair and reuse.
  63. Fillion Raymond A. (Schenectady NY) Cole ; Jr. Herbert S. (Burnt Hills NY), Reconstructable interconnect structure for electronic circuits.
  64. Yerman Alexander J. (Scotia NY), Screenable power chip mosaics, a method for fabricating large power semiconductor chips.
  65. Shimizu Yoshio (Kitakyushu JPX) Kotani Shoji (Kitakyushu JPX) Kawaguchi Masatugi (Kitakyushu JPX), Semiconductor device having a mechanical buffer.
  66. Mori Katsunobu (Nara JPX), Semiconductor device having external electrodes formed in concave portions of an anisotropic conductive film.
  67. Tsuji Kazuto (Kawasaki JPX) Yoneda Yoshiyuki (Kawasaki JPX) Kasai Junichi (Kawasaki JPX) Sono Michio (Kawasaki JPX), Semiconductor device having improved leads comprising palladium plated nickel.
  68. Kotani Jutaro (Takatsuki JPX) Ihara Masahiro (Takatsuki JPX) Nakura Hideaki (Hirakata JPX) Yokozawa Masami (Yawata JPX), Semiconductor device including an electrode.
  69. Greer Stuart E. (Austin TX), Semiconductor device solder bump having intrinsic potential for forming an extended eutectic region and method for makin.
  70. Sudo Toshio (Kawasaki JPX), Semiconductor integrated circuit device with optical transmit-receive means.
  71. van der Have Leonard A. (Ames IA), Semiconductor integrated circuit fabrication yield improvements.
  72. Butt Sheldon H. (Godfrey IL), Semiconductor package.
  73. Butt Sheldon H. (Godfrey IL), Semiconductor package.
  74. Adams Victor J. (Tempe AZ) Bennett Paul T. (Phoenix AZ) Hughes Henry G. (Scottsdale AZ) Scofield ; Jr. Brooks L. (Tempe AZ) Stuckey Marilyn J. (Phoenix AZ), Semiconductor wafer level package.
  75. Abbott Donald C. (Norton MA) Fritzsche Robert M. (Attleboro Falls MA), Silver spot/palladium plate lead frame finish.
  76. Yung Edward K. (Carrboro NC), Solder bump including circular lip.
  77. Moore Kevin D. (Schaumburg IL) Missele Carl (Elgin IL), Solder bumping of integrated circuit die.
  78. Reid Lee R. (Plano TX), Solid state interconnection system for three dimensional integrated circuit structures.
  79. Ludwig David E. (Irvine CA) Saunders Christ H. (Laguna Niguel CA) Some Raphael R. (Williston VT) Stuart John J. (Newport Beach CA), Stack of IC chips in lieu of single IC chip.
  80. Beaman Brian S. (Hyde Park NY) Doany Fuad E. (Katonah NY) Fogel Keith E. (Bardonia NY) Hedrick ; Jr. James L. (Oakland CA) Lauro Paul A. (Nanuet NY) Norcott Maurice H. (Valley Cottage NY) Ritsko John, Three dimensional high performance interconnection package.
  81. Nicewarner ; Jr. Earl R. (Gaithersburg MD), Three-dimensional modular assembly of integrated circuits.
  82. Farnworth Warren M. ; Akram Salman, Use of palladium in IC manufacturing.

이 특허를 인용한 특허 (95)

  1. Lee, Jin-Yuan; Lo, Hsin-Jung, Chip assembly with interconnection by metal bump.
  2. Lin, Mou-Shiung; Lee, Jin-Yuan, Chip packages having dual DMOS devices with power management integrated circuits.
  3. Lin,Mou Shiung, Chip structure with redistribution traces.
  4. Akram, Salman, Copper interconnect.
  5. Akram,Salman, Copper interconnect.
  6. Akram,Salman, Copper interconnect.
  7. Akram,Salman, Copper interconnect for semiconductor device.
  8. Veychard, Damien; Quercia, Fabien; Perriaud, Eric, Copper wire receiving pad.
  9. Hosseini, Khalil; Stecher, Matthias, Electronic device and method for production.
  10. Hosseini, Khalil; Stecher, Matthias, Electronic device and method for production.
  11. Lim,Victor Seng Keong; Zhang,Fan; Lam,Jeffrey, Elevated bond-pad structure for high-density flip-clip packaging and a method of fabricating the structures.
  12. Sutardja,Sehat; Wu,Albert; Lee,Jin Yuan; Lin,Mou Shiung, Fabrication of wire bond pads over underlying active devices, passive devices and/or dielectric layers in integrated circuits.
  13. Lin, Mou-Shiung, High performance system-on-chip inductor using post passivation process.
  14. Lin, Mou-Shing, High performance system-on-chip using post passivation process.
  15. Lin, Mou-Shiung, High performance system-on-chip using post passivation process.
  16. Tellkamp,John P., Metallic strain-absorbing layer for improved fatigue resistance of solder-attached devices.
  17. Akram, Salman, Method and semiconductor device having copper interconnect for bonding.
  18. Lin, Mou-Shiung; Lee, Jin-Yuan, Method for making high-performance RF integrated circuits.
  19. Lin, Mou-Shiung; Lee, Jin-Yuan, Method for making high-performance RF integrated circuits.
  20. Akram, Salman, Method of improving copper interconnects of semiconductor devices for bonding.
  21. Akram,Salman, Method of improving copper interconnects of semiconductor devices for bonding.
  22. Lee, Jin Yuan; Chen, Ying Chih; Lin, Mou Shiung, Method of wire bonding over active area of a semiconductor circuit.
  23. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  24. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  25. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  26. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  27. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  28. Lee, Jin-Yuan; Chen, Ying-chih, Method of wire bonding over active area of a semiconductor circuit.
  29. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection process and structures.
  30. Lin, Mou Shiung; Lee, Jin Yuan, Post passivation interconnection schemes on top of IC chip.
  31. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  32. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  33. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  34. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  35. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  36. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  37. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chip.
  38. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chip.
  39. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chip.
  40. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chip.
  41. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chip.
  42. Lin, Mou Shiung; Lee, Jin Yuan, Post passivation interconnection schemes on top of IC chips.
  43. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chips.
  44. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chips.
  45. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chips.
  46. Lin, Mou-Shiung, Post passivation interconnection schemes on top of the IC chips.
  47. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection schemes on top of the IC chips.
  48. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection schemes on top of the IC chips.
  49. Lin,Mou Shiung, Post passivation interconnection schemes on top of the IC chips.
  50. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Post passivation interconnection schemes on top of the IC chips.
  51. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Post passivation interconnection schemes on top of the IC chips.
  52. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Post passivation interconnection schemes on top of the IC chips.
  53. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of the IC chips.
  54. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of the IC chips.
  55. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of the IC chips.
  56. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of the IC chips.
  57. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection structures.
  58. Lin, Mou-Shiung; Lee, Jin-Yuan; Lei, Ming-Ta; Huang, Ching-Cheng, Post passivation metal scheme for high-performance integrated circuit devices.
  59. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation method for semiconductor chip or wafer.
  60. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation structure for semiconductor chip or wafer.
  61. Lin, Mou-Shiung; Lee, Jin-Yuan, Semiconductor chip structure.
  62. Ellis,Timothy W.; Murdeshwar,Nikhil; Eshelman,Mark A.; Rheault,Christian, Semiconductor copper bond pad surface protection.
  63. Akram, Salman, Semiconductor device having copper interconnect for bonding.
  64. Hung, Sung-Ching; Huang, Wen-Pin, Semiconductor package.
  65. Zhu, Jianxin; Sluzewski, David A.; Stover, Lance E.; Hoehn, Joel W.; Schulz, Kevin J., Top bond pad for transducing head interconnect.
  66. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  67. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  68. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  69. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  70. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  71. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  72. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  73. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  74. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  75. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  76. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  77. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  78. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  79. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  80. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  81. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  82. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  83. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  84. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  85. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  86. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  87. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  88. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Top layers of metal for integrated circuits.
  89. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Top layers of metal for integrated circuits.
  90. Lin, Mou-Shiung; Wei, Gu-Yeon, Voltage regulator integrated with semiconductor chip.
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  92. Lin,Mou Shiung; Chen,Michael; Chou,Chien Kang; Chou,Mark, Wirebond pad for semiconductor chip or wafer.
  93. Gleixner, Robert J.; Danielson, Donald; Paluda, Patrick M.; Naik, Rajan, Wirebond structure and method to connect to a microelectronic die.
  94. Gleixner, Robert J.; Danielson, Donald; Paluda, Patrick M.; Naik, Rajan, Wirebond structure and method to connect to a microelectronic die.
  95. Gleixner,Robert J.; Danielson,Donald; Paluda,Patrick M.; Naik,Rajan, Wirebond structure and method to connect to a microelectronic die.
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