초록 ▼

The method and apparatus of the present invention is directed to architectures for signal processing, such as for performing analog-to-digital and digital-to-analog conversions, in which the source signal is decomposed into subband signals by an analysis filter, processed, and the processed subband

The method and apparatus of the present invention is directed to architectures for signal processing, such as for performing analog-to-digital and digital-to-analog conversions, in which the source signal is decomposed into subband signals by an analysis filter, processed, and the processed subband signals combined to form a reconstructed signal that is representative of the source signal.

대표청구항 ▼

The method and apparatus of the present invention is directed to architectures for signal processing, such as for performing analog-to-digital and digital-to-analog conversions, in which the source signal is decomposed into subband signals by an analysis filter, processed, and the processed subband

The method and apparatus of the present invention is directed to architectures for signal processing, such as for performing analog-to-digital and digital-to-analog conversions, in which the source signal is decomposed into subband signals by an analysis filter, processed, and the processed subband signals combined to form a reconstructed signal that is representative of the source signal. 8. A timing apparatus, comprising: having a first a gear having a first face, a second face, an outer toothed portion having a first width, an inner web portion having a second width less than the first width, such that the gear has a generally cylindrical recess on the first face of the gear; and a timing ring being secured within the recess. 19. A method of manufacturing a timing apparatus, comprising: providing a gear having a face, and outer toothed portion, and a recess formed in the face; positioning a timing ring within the recess; and securing the positioned timing ring to the gear within the recess. 20. The method of claim 19 wherein the timing ring comprises an annular member having plurality of projecting timing teeth. 21. The method of claim 20 wherein the securing step includes securing the timing ring in the recess such that the timing teeth are arranged radially inwardly of the outer toothed portion of the gear. 22. The method of claim 21 wherein the securing step includes securing the timing ring in the recess such that the timing teeth project radially inwardly. 23. The method of claim 19 wherein the securing step includes securing the timing ring in the recess using an adhesive compound. 24. The method of claim 19 wherein the securing step includes securing the timing ring in the recess using a push fit arrangement. 25. The method of claim 19 wherein the recess is generally cylindrical. said differential input circuit consists of two depletion MOS transistors for receiving the differential voltage signal applied thereto, respectively. 7. The transconductance amplifier as claimed in claim 1, wherein said differential input circuit consists of first and second transistors with gates connected respectively to first and second amplifier input terminals and with sources connected together to the ground or the voltage source. 8. The transconductance amplifier as claimed in claim 1, wherein each pair of said first, second and third pairs of regulated cascode circuits consist of an operational amplifier and a transistor with a gate connected to an output terminal of said operational amplifier. 9. The transconductance amplifier as claimed in claim 1, wherein said first pair of regulated cascode circuits consist of third and fourth transistors with sources connected respectively to output terminals of said differential input circuit, a first operational amplifier with a non-inverting input terminal connected to a control terminal which receives the control voltage for controlling a conductance Gm, with an inverting input terminal connected to a source of said third transistor and with an output terminal connected to a gate of said third transistor, and a second operational amplifier with a non-inverting input terminal connected to said control terminal, with an inverting input terminal connected to a source of said fourth tr