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In a programmable logic device having dedicated multiplier circuitry, some of the scan chain registers normally used for testing the device are located adjacent input registers of the multipliers. Those scan chain registers are ANDed with the input registers, and can be loaded with templates of ones

In a programmable logic device having dedicated multiplier circuitry, some of the scan chain registers normally used for testing the device are located adjacent input registers of the multipliers. Those scan chain registers are ANDed with the input registers, and can be loaded with templates of ones and zeroes. This allows, e.g., subset multiplication if the least significant bits are loaded with zeroes and the remaining bits are loaded with ones. The multipliers preferably are arranged in blocks with other components, such as adders, that allow them to be configured as finite impulse response (FIR) filters. In such configurations, the scan chain registers can be used to load filter coefficients, avoiding the use of scarce logic and routing resources of the device.

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In a programmable logic device having dedicated multiplier circuitry, some of the scan chain registers normally used for testing the device are located adjacent input registers of the multipliers. Those scan chain registers are ANDed with the input registers, and can be loaded with templates of ones

In a programmable logic device having dedicated multiplier circuitry, some of the scan chain registers normally used for testing the device are located adjacent input registers of the multipliers. Those scan chain registers are ANDed with the input registers, and can be loaded with templates of ones and zeroes. This allows, e.g., subset multiplication if the least significant bits are loaded with zeroes and the remaining bits are loaded with ones. The multipliers preferably are arranged in blocks with other components, such as adders, that allow them to be configured as finite impulse response (FIR) filters. In such configurations, the scan chain registers can be used to load filter coefficients, avoiding the use of scarce logic and routing resources of the device. x et al., 324/073; US-4710861, 19871200, Kanner; US-4940929, 19900700, Williams; US-4952863, 19900800, Sartwell et al.; US-5059889, 19911000, Heaton, 323/275; US-5103388, 19920400, Williams et al.; US-5130635, 19920700, Kase; US-5686820, 19971100, Riggio, Jr.; US-5712774, 19980100, Uramoto; US-5757203, 19980500, Brown; US-5773990, 19980600, Wilstrup et al.; US-5789933, 19980800, Brown et al.; US-5789934, 19980800, Kolkowski et al.; US-5886892, 19990300, Radley et al.; US-5914870, 19990600, Noble et al.; US-5917318, 19990600, Kamata; US-5925278, 19990700, Hirst; US-5932996, 19990800, Liepe et al.; US-6046577, 20000400, Rincon-Mora et al.; US-6087843, 20000700, Pun et al. ctromagnetic waves emitted by the transmitter antenna. 26. A method for logging electrical properties in a geological formation during drilling of a well by a drillstring with an outer metallic surface, comprising the steps of: emitting from a transmitter antenna positioned outside the drillstring's outer metallic surface a first series of electromagnetic waves guided along the drillstring at a first time and a second series of electromagnetic waves guided along the drillstring at a second time; receiving a series of reflected electromagnetic waves in a receiver antenna positioned outside the drillstring's outer metallic surface, wherein the emitted first and second series of electromagnetic waves are canceled in the receiver antenna by a canceling device; transforming the received se