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High speed peripheral interconnect apparatus, method and system 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-013/38
출원번호 US-0747422 (2000-12-22)
발명자 / 주소
  • Riley, Dwight
  • Pettey, Christopher J.
출원인 / 주소
  • Hewlett-Packard Development Company, L.P.
대리인 / 주소
    Akin Gump Strauss Hauer & Feld LLP
인용정보 피인용 횟수 : 30  인용 특허 : 44

초록

A high speed connection apparatus, method, and system is provided for peripheral components on digital computer systems. The peripheral component interconnect (PCI) specification is used as a baseline for an extended set of commands and attributes. The extended command and the attribute are issued o

대표청구항

A high speed connection apparatus, method, and system is provided for peripheral components on digital computer systems. The peripheral component interconnect (PCI) specification is used as a baseline for an extended set of commands and attributes. The extended command and the attribute are issued o

이 특허에 인용된 특허 (44)

  1. Peres Mauricio,CAX ; Salemi Hojjat,CAX ; Laurence Michel,CAX, ATM cell transmit priority allocator.
  2. Hewitt Larry D. ; Swanstrom Scott E., Bus arbiter including programmable request latency counters for varying arbitration priority.
  3. Bennett Brian R. (Laguna Niguel CA), Bus control system and method that selectively generate an early address strobe.
  4. Levy John V. (Palo Alto CA) Rodgers David P. (Acton MA) Stewart Robert E. (Stow MA) Casabona Richard J. (Stow MA), Bus for a data processing system with overlapped sequences.
  5. Olson Anthony M. (Stevensville MI), CPU lock logic for corrected operation with a posted write array.
  6. Bagnoli Carlo (Milan ITX) Perrella Guido (Pescara ITX) Majo Tommaso (Paderno Dugnano ITX), Centralized arbitration system using the status of target resources to selectively mask requests from master units.
  7. Makris Perry (Fairfax VA) Choi Frederick (Herndon VA) Klimek Mark (Centreville VA) Mapp James (Herndon VA) Munemoto Koji (Herndon VA) Nicoll Jeff (Chantilly VA) Soderberg Mark (Sterling VA) Moore Jam, Communication processor for a packet-switched network.
  8. Chen Chang-Lung (Hsing-Chu TWX), Data bus arbitration for split transaction computer bus.
  9. Mery Lionel (Paris FRX) Guyon Jean-Paul (Chaville FRX) Catorc Jacqueline (Villejuif FRX), Data transfer arrangement permitting variable rate data transfer between a modem and a synchronous terminal.
  10. Hausauer Brian S. ; Pettey Christopher J. ; Seeman Thomas R., Delayed transaction protocol for computer system bus.
  11. Callison Ryan A. ; Chard Gary F., Disk array controller for performing exclusive or operations.
  12. Chandler Gregory T. (Houston TX) Grieff Thomas W. (Spring TX) Callison Ryan A. (Spring TX), Disk array controller having command descriptor blocks utilized by bus master and bus slave for respectively performing.
  13. Callison Ryan A. (Spring TX) Chandler Gregory T. (Houston TX) Grieff Thomas W. (Spring TX), Disk array controller having internal protocol for sending address/transfer count information during first/second load c.
  14. Guthrie Guy Lynn ; Kelley Richard Allen ; Neal Danny Marvin ; Thurber Steven Mark, Enhanced dual speed bus computer system.
  15. Johnson Leith L. (Fort Collins CO) Carlson Richard (Fort Collins CO), Enhanced peripheral component interconnect bus protocol.
  16. Olarig Sompong P., Fault-tolerant interconnection means in a computer system.
  17. Riley Dwight ; Pettey Christopher J., High speed peripheral interconnect apparatus, method and system.
  18. Munoz-Bustamante Carlos ; Pearce Jerry William, Interoperable 33 MHz and 66 MHz devices on the same PCI bus.
  19. McFarland Harold L. (San Jose CA), Interrupt control for multiprocessor computer system.
  20. Grieff Thomas W. ; Galloway William C. ; Carlson Jeff M., Locked exchange FIFO.
  21. Gulick Dale E., Method and apparatus for clock synchronization across an isochronous bus by adjustment of frame clock rates.
  22. Wolford Jeff W. (Spring TX) Fry Walter G. (Spring TX), Method and apparatus for concurrency of bus operations.
  23. Moyer William C. (Dripping Springs TX) Gullette James B. (Austin TX) Garcia Michael J. (Austin TX), Method and apparatus for performing bus arbitration in a data processing system.
  24. Solari Edward (Monmouth OR), Method and apparatus for priority selection of commands.
  25. Amini Nader (Boca Raton FL) Kohli Ashu (Delray Beach FL), Method and apparatus for providing back-to-back data transfers in an information handling system having a multiplexed bu.
  26. Bomba Frank C. (Andover MA) Jenkins Stephen R. (Acton MA), Method and apparatus for requesting service of interrupts by selected number of processors.
  27. Benton Michael K. (Malvern PA) Gold Anthony P. (Wayne PA) Schranz Richard A. (Norristown PA), Method and apparatus for simultaneous interconnection of multiple requestors to multiple memories.
  28. Glaser Stephen D. (Berlin MA) Thomas Robert E. (Hudson MA) Walsh Robert J. (Ashland MA), Method and apparatus for transporting timed program data using single transport schedule.
  29. Flannery Michael R., Method and apparatus of providing power management using a self-powered universal serial bus (USB) device.
  30. Schmenk David S. (The Woodlands TX) Grant David L. (Houston TX) Schultz Stephen M. (Houston TX) Neufeld E. David (Tomball TX) Flower David L. (Tomball TX), Method for controlling disk array operations by receiving logical disk requests and translating the requests to multiple.
  31. Cook Sherri E. (Boca Raton FL) McNeill ; Jr. Andrew B. (Deerfield Beach FL), Method for selecting transmission speeds for transmitting data packets over a serial bus.
  32. Bush Kenneth L. (Cypress TX) Perry Ralph S. (Houston TX) Grieff Thomas W. (Houston TX) Scholhamer George J. (Houston TX), Mode-selectable integrated disk drive for computer.
  33. Matelan M. Nicholas (Dallas TX) Leete Thomas G. (Plano TX) Zsohar Leslie (Carrollton TX) Blanchard Michael K. (Bedford TX) Naeini Abdolreza (Carrollton TX) Hsu Jacob (Farmers Branch TX) Smith Dennis , Multicomputer digital processing system.
  34. Edem Brian C. (San Jose CA) Worsley Debra J. (Sunnyvale CA), Network for transmitting isochronous-source data using a frame structure with variable number of time slots to compensat.
  35. Melo Maria L. ; Alzien Khaldoun, PCI to PCI bridge for transparently completing transactions between agents on opposite sides of the bridge.
  36. Heil Thomas F. (Easley SC), Peripheral component interconnect special cycle protocol using soft message IDS.
  37. Patterson Garvin Wesley (Glendale AZ) Shelly William A. (Phoenix AZ) Calle Jaime (Glendale AZ) Monahan Earnest M. (Phoenix AZ), Programmable interface apparatus and method.
  38. Bissett Thomas D. (Derry NH) Bruckert William (Northboro MA) Thirumalai Ajai (Marlboro MA) Amirmokri Jay (Lowell MA), Protocol for transfer of DMA data.
  39. Tipley Roger E. (Houston TX), Split transaction protocol for the peripheral component interconnect bus.
  40. Whipple David L. (Braintree MA), System bus means for inter-processor communication.
  41. Lory Jay R. ; Pecone Victor K., System for preemptive bus master termination by determining termination data for each target device and periodically ter.
  42. Yasui Takashi (Kobe JPX) Fukushima Masanobu (Toyonaka JPX) Hara Kazuhiko (Takatsuki JPX), System with selectively exclusionary enablement for plural indirect address type interrupt control circuit.
  43. Alzien Khaldoun, Transparent PCI to PCI bridge with dynamic memory and I/O map programming.
  44. Miller John ; Taylor Kit ; Tolmich Ira, Vending machine controller and system.

이 특허를 인용한 특허 (30)

  1. Pavesi,Marco; Grassi,Maurizio; De Pieri,Fabio; Ferloni,Mauro; Gemelli,Riccardo, Clock generation system for a prototyping apparatus.
  2. Hamilton, Keith S.; Jamieson, Steve; Long, Joe D.; Oeuvray, Paul M., Component aliasing operating within a component-based computing system.
  3. Nakayama, Keishi; Uehara, Keitaro; Aoyagi, Takashi; Toya, Shinichiro, Computer system and bus assignment method.
  4. Nakayama, Keishi; Uehara, Keitaro; Aoyagi, Takashi; Toya, Shinichiro, Computer system and bus assignment method.
  5. Riley, Dwight; Pettey, Christopher J., Device adapted to send information in accordance with a communication protocol.
  6. Riley,Dwight; Pettey,Christopher J., Device operating according to a communication protocol.
  7. Riley,Dwight D., Distributed peer-to-peer communication for interconnect busses of a computer system.
  8. Riley,Dwight D., Distributed peer-to-peer communication for interconnect busses of a computer system.
  9. Bell,Shane L., Efficient detection of multiple assertions in a bus.
  10. Shah, Paras A.; Waldrop, Timothy K., Enhancing a PCI-X split completion transaction by aligning cachelines with an allowable disconnect boundary's ending address.
  11. Allen,James W.; Mayfield,Michael John; Ng,Alvan Wing, Fixed snoop response time for source-clocked multiprocessor busses.
  12. Pettey,Christopher J.; Riley,Dwight, High speed peripheral interconnect apparatus, method and system.
  13. Thurlo,Clark S.; Hawthorne, III,Lorenza L., Method and apparatus for detecting a device's ability to run at a selected frequency in a PCI non-inhibit bus-connect mode.
  14. Riley, Dwight D., Method and apparatus for setting a primary port on a PCI bridge.
  15. Naveh,Alon; Surgutchik,Roman; Gunther,Stephen H.; Greiner,Robert; Ma,Hung Piao; Dai,Kevin; Wong,Keng, Method and apparatus to dynamically change an operating frequency and operating voltage of an electronic device.
  16. Naveh,Alon; Surgutchik,Roman; Gunther,Stephen H.; Greiner,Robert; Ma,Hung Piao; Dai,Kevin; Wong,Keng L., Method and apparatus to dynamically change an operating frequency and operating voltage of an electronic device.
  17. Hamilton,Keith S.; Jamieson,Steve, Method and system for application partitions.
  18. Bolen,Austin P.; Khatri,Mukund P.; Wynn,Allen C., Method and system for remote or local access to keyboard control in legacy USB mode with a UHCI USB controller.
  19. Bolen,Austin P.; Khatri,Mukund P.; Wynn,Allen C., Method for selecting local or remote keyboard control in legacy USB mode within predetermined time.
  20. Chan,Michael Y.; Riley,Dwight D., Point-to-point electrical loading for a multi-drop bus.
  21. Riley,Dwight D., Power management state distribution using an interconnect.
  22. Keller, James B.; Subramanian, Sridhar P.; Gunna, Ramesh, Retry mechanism.
  23. Keller, James B.; Subramanian, Sridhar P.; Gunna, Ramesh, Retry mechanism.
  24. Fukushima, Keito, Service usage terminal, service providing terminal, control method of service providing terminal, control method of service providing terminal and service providing system.
  25. Moertl, Daniel Frank; Yanes, Adalberto Guillermo, Split completion performance of PCI-X bridges based on data transfer amount.
  26. Riley, Dwight D., System and method for a hierarchical interconnect network.
  27. Riley, Dwight D., System and method for multi-host sharing of a single-host device.
  28. Riley, Dwight D., System and method for remote direct memory access over a network switch fabric.
  29. Hamilton,Keith S.; Jamieson,Steve, System determining whether to activate public and private components operating within multiple applications of a component-based computing system.
  30. Zink, Daniel J., System enabling automatic error detection in response to removal of bus adapter.
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