초록 ▼

A process for forming fusible links in an integrated circuit includes forming the fusible link in the last metallization layer. The process can be employed in the fabrication of integrated circuits employing copper metallization and low k dielectric materials. The fusible link is formed in the last

A process for forming fusible links in an integrated circuit includes forming the fusible link in the last metallization layer. The process can be employed in the fabrication of integrated circuits employing copper metallization and low k dielectric materials. The fusible link is formed in the last metallization layer and may be formed simultaneously with the bonding pad areas.

대표청구항 ▼

1. A process for forming a fusible link in an integrated circuit comprising: forming a second dielectric layer on a planarized surface of an underlying metal interconnect and first dielectric layer, wherein the first and the second dielectric layers have a dielectric constant less than about 3.0,

1. A process for forming a fusible link in an integrated circuit comprising: forming a second dielectric layer on a planarized surface of an underlying metal interconnect and first dielectric layer, wherein the first and the second dielectric layers have a dielectric constant less than about 3.0, and wherein the underlying metal interconnect comprises copper; depositing an oxide layer at a thickness effective to prevent cracking of the oxide layer during a laser fuse process; forming a via in the oxide layer and second dielectric layer extending to the underlying metal interconnect; filling the via with a conductive metal; forming a final metal layer; patterning the final metal layer to form a fusible link, a bonding pad area and wiring; depositing a passivation layer, and patterning the passivation layer to simultaneously remove the passivation layer from the bonding pad area and a portion of the fusible link, wherein surfaces of the fusible link and the bonding pad area are exposed. 2. The process according to claim 1, wherein the final metal layer comprises an aluminum metal. 3. The process according to claim 1 wherein the via metal and the final metal layer comprise an aluminum metal. 4. The process according to claim 1, wherein the first dielectric layer comprises a layer of SILK.RTM.. 5. The process according to claim 1 further comprising depositing a barrier layer in the via prior to filling the via with the metal.