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Modified pad for copper/low-k 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01R-009/00
출원번호 US-0777302 (2001-02-06)
발명자 / 주소
  • Chen, Sheng-Hsiung
  • Chen, Shun Long
  • Lin, Hungtse
출원인 / 주소
  • Taiwan Semiconductor Manufacturing Company
대리인 / 주소
    Saile, George O.Ackerman, Stephen B.Stanton, Stephen G.
인용정보 피인용 횟수 : 33  인용 특허 : 8

초록

A method to fabricate a bonding pad structure including the following steps. A substrate having a top metal layer and a passivation layer overlying the top metal layer is provided. The top metal layer being electrically connected to a lower metal layer by at least one metal via within a metal via ar

대표청구항

A method to fabricate a bonding pad structure including the following steps. A substrate having a top metal layer and a passivation layer overlying the top metal layer is provided. The top metal layer being electrically connected to a lower metal layer by at least one metal via within a metal via ar

이 특허에 인용된 특허 (8)

  1. Shiue Ruey-Yun,TWX ; Wu Wen-Teng,TWX ; Shieh Pi-Chen,TWX ; Liu Chin-Kai,TWX, Bond pad structure for the via plug process.
  2. Yu Chen Hua,TWX, Bonds pads equipped with heat dissipating rings and method for forming.
  3. Galloway Terry R., Extended bond pads with a plurality of perforations.
  4. Chen Kun-Cho,TWX ; Jenq Jason,TWX, Method and structure for preventing bonding pad peel back.
  5. Chen C. H.,TWX ; Chao Y. C.,TWX ; Tsui Y. M.,TWX ; Chang W. R.,TWX, Method for formingzig-zag bordered openings in semiconductor structures.
  6. Hayashi Jun (Tokyo JPX) Yamanaka Michiko (Tokyo JPX), Semiconductor device and fabrication process therefor.
  7. Yiu Ho-Yin,HKX ; Wu Lin-June,TWX ; Chen Bor-Cheng,TWX ; Horng Jan-Her,TWX, Stress buffered bond pad and method of making.
  8. Moslehi Mehrdad M., Ultra high-speed chip semiconductor integrated circuit interconnect structure and fabrication method using free-space dielectrics.

이 특허를 인용한 특허 (33)

  1. Luce,Stephen E.; McDevitt,Thomas L.; Stamper,Anthony K., Bilayer aluminum last metal for interconnects and wirebond pads.
  2. Hsia, Chin Chiu; Yao, Chih Hsiang; Huang, Tai Chun; Peng, Chih Tang, Bond pad structure for wire bonding.
  3. Lin,Mou Shiung, Chip structure with redistribution traces.
  4. Chen, Hsien-Wei; Liu, Yu-Wen; Tsai, Hao-Yi; Jeng, Shin-Puu; Chen, Ying-Ju, Double solid metal pad with reduced area.
  5. Chen, Hsien-Wei; Liu, Yu-Wen; Tsai, Hao-Yi; Jeng, Shin-Puu; Chen, Ying-Ju, Double solid metal pad with reduced area.
  6. Horng, Shean-Ren; Hou, Kuo-Nan; Lai, Feng-Liang, Flexible processing method for metal-insulator-metal capacitor formation.
  7. Huang, Tzu Hsin; Tsau, Liming; Chen, Vincent, Metal bond pad for integrated circuits allowing improved probing ability of small pads.
  8. Yoo,Seung Jong, Method for forming semiconductor device bonding pads.
  9. Lee, Jin Yuan; Chen, Ying Chih; Lin, Mou Shiung, Method of wire bonding over active area of a semiconductor circuit.
  10. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  11. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  12. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  13. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  14. Lee, Jin-Yuan; Chen, Ying-chih, Method of wire bonding over active area of a semiconductor circuit.
  15. Lin, Mou-Shiung, Post passivation interconnection schemes on top of the IC chips.
  16. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection schemes on top of the IC chips.
  17. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection schemes on top of the IC chips.
  18. Lin,Mou Shiung, Post passivation interconnection schemes on top of the IC chips.
  19. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Post passivation interconnection schemes on top of the IC chips.
  20. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Post passivation interconnection schemes on top of the IC chips.
  21. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Post passivation interconnection schemes on top of the IC chips.
  22. Tomimori, Hiroaki; Aoki, Hidemitsu; Mikagi, Kaoru; Furuya, Akira; Tao, Tetsuya, Process for making a semiconductor device having a roughened surface.
  23. Zeng, Xiang Yin; Cui, Ming Dong; Christensen, Gregory V.; Abdulla, Mostafa Naguib; Lu, Daoqiang; He, Jiangqi; Tang, Jiamiao, Reducing input capacitance of high speed integrated circuits.
  24. Tsao,Pei Haw; Huang,Chender; Hou,Shang Yu; Su,Chao Yuan; Hsu,Chia Hsiung, Semiconductor bond pad structures and methods of manufacturing thereof.
  25. Huang,Tai Chun; Yao,Chih Hsiang; Chi,Kuan Shou; Lei,Ming Ta; Hsia,Chin Chiu, Semiconductor bonding pad structure.
  26. Hatano, Masaaki; Usui, Takamasa, Semiconductor device.
  27. Tomimori,Hiroaki; Aoki,Hidemitsu; Mikagi,Kaoru; Furuya,Akira; Tao,Tetsuya, Semiconductor device having a roughened surface.
  28. Matsubara,Yoshihisa, Semiconductor device having bonding pad above low-k dielectric film.
  29. Matsuoka, Takeru; Fujiki, Noriaki; Takewaka, Hiroki, Semiconductor device including copper interconnect line and bonding pad, and method of manufacturing the same.
  30. Hong, Jongwon; Kim, Hei Seung; Nam, Kyoung Hee; Lee, Jongmyeong; Choi, Gilheyun, Semiconductor devices including a non-planar conductive pattern, and methods of forming semiconductor devices including a non-planar conductive pattern.
  31. Horng, Shean-Ren; Hou, Kuo-Nan; Lai, Feng-Liang, Semiconductor metal insulator metal capacitor device and method of manufacture.
  32. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Top layers of metal for integrated circuits.
  33. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Top layers of metal for integrated circuits.
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