Voltage detecting device, battery remaining voltage detecting device, voltage detecting method, battery remaining voltage detecting method, electronic timepiece and electronic device
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G04B-001/00
G04B-009/00
출원번호
US-0718750
(2000-11-22)
우선권정보
JP-0375879 (1999-11-24); JP-0188170 (2000-06-22)
발명자
/ 주소
Nakamiya, Shinji
출원인 / 주소
Seiko Epson Corporation
대리인 / 주소
Watson, Mark P.
인용정보
피인용 횟수 :
13인용 특허 :
3
초록▼
A voltage detection and a remaining battery voltage display for a secondary power source so as to notify the user of the remaining battery voltage of the secondary power source at the optimal timing and in an accurate manner. A voltage correlated to the power source capacity of the secondary power s
A voltage detection and a remaining battery voltage display for a secondary power source so as to notify the user of the remaining battery voltage of the secondary power source at the optimal timing and in an accurate manner. A voltage correlated to the power source capacity of the secondary power source is detected as a detection voltage. The detection voltage is directly output if a rapid charging is not being detected. If the rapid charging is being detected, the detection voltage is output after being corrected for an amount of the apparent voltage boost which occurs in the secondary power source due to the rapid charging. The detection voltage thus obtained is compared with a predetermined reference voltage so as to discriminate the remaining capacity of the secondary power source.
대표청구항▼
A voltage detection and a remaining battery voltage display for a secondary power source so as to notify the user of the remaining battery voltage of the secondary power source at the optimal timing and in an accurate manner. A voltage correlated to the power source capacity of the secondary power s
A voltage detection and a remaining battery voltage display for a secondary power source so as to notify the user of the remaining battery voltage of the secondary power source at the optimal timing and in an accurate manner. A voltage correlated to the power source capacity of the secondary power source is detected as a detection voltage. The detection voltage is directly output if a rapid charging is not being detected. If the rapid charging is being detected, the detection voltage is output after being corrected for an amount of the apparent voltage boost which occurs in the secondary power source due to the rapid charging. The detection voltage thus obtained is compared with a predetermined reference voltage so as to discriminate the remaining capacity of the secondary power source. ge state and a gate. A gate bias circuit on the integrated circuit is coupled to the gates of the memory cells. The gate bias circuit includes at least a read voltage and a margin voltage. A detection circuit on the integrated circuit is coupled to the cells. The detection circuit includes a comparator and a reference voltage. The reference voltage and the voltage state of one of the cells are coupled to the comparator. The detection circuit includes an output generating a signal corresponding to the comparator output. The integrated circuit includes a monitor circuit. The monitor circuit is coupled to the output of the detection circuit and determines whether the voltage state of the cell transitions between application of the read and margin voltages to the gate. et al., 395/183.14; US-5537585, 19960700, Blickenstaff et al., 395/600; US-5537618, 19960700, Boulton et al., 395/161; US-5547154, 19960800, Kirchoff et al., 248/118.3; US-5547272, 19960800, Paterson et al., 312/223.2; US-5564054, 19961000, Bramnick et al., 395/700; US-5592362, 19970100, Ohgami et al., 361/686; US-5596481, 19970100, Liu et al., 361/683; US-5596482, 19970100, Horikoshi, 361/683; US-5627964, 19970500, Reynolds et al., 395/183.22; US-5649200, 19970700, Leblang et al., 717/122; US-5668992, 19970900, Hammer et al., 395/651; US-5678002, 19971000, Fawcett et al., 395/575; US-5680640, 19971000, Ofek et al., 395/839; US-5689253, 19971100, Hargreaves et al., 341/022; US-5689706, 19971100, Rao et al., 395/617; US-5694293, 19971200, Seto et al., 361/687; US-5708776, 19980100, Kikinis, 395/185.08; US-5708812, 19980100, Van Dyke et al., 395/712; US-5724224, 19980300, Howell et al., 361/680; US-5727163, 19980300, Bezos, 395/227; US-5732268, 19980300, Bizzarri, 395/652; US-5748877, 19980500, Dollahite et al., 395/183.12; US-5759644, 19980600, Stanley, 428/014; US-5768370, 19980600, Maatta et al., 379/433; US-5775822, 19980700, Cheng, 400/489; US-5778372, 19980700, Cordell et al., 707/100; US-5790796, 19980800, Sadowsky, 395/200.51; US-5796579, 19980800, Nakajima et al., 361/683; US-5797281, 19980800, Fox, 063/012; US-5803416, 19980900, Hanson et al., 248/118; US-5805882, 19980900, Cooper et al., 395/652; US-5809248, 19980900, Vidovic, 395/200.49; US-5809511, 19980900, Peake, 707/204; US-5818635, 19981000, Hohn et al., 359/612; US-5819274, 19981000, Jackson, Jr., 707/010; US-5825355, 19981000, Palmer et al., 345/336; US-5825506, 19981000, Bednar et al., 358/402; US-5826839, 19981000, Chen, 248/118; US-5832522, 19981100, Blickenstaff et al., 707/204; US-5835344, 19981100, Alexander, 361/683; US-5845136, 19981200, Babc
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이 특허에 인용된 특허 (3)
Seong Hwan-Ho (Seoul KRX) Im Sang-Tae (Kyungki-do KRX), Battery charging circuit with charging rate control.
Nakamura, Hidenori; Koike, Kunio; Shimizu, Eisaku, Electronically controlled timepiece, and power supply control method and time correction method therefore.
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