초록 ▼

A double-barreled syringe is provided which includes a mixing tip which is detachable after the tip is locked to the syringe body, so that the tip may be replaced by a locking cap. Locking occurs when a neck extending from the body between two shoulders is inserted into a bore in the tip (or, altern

A double-barreled syringe is provided which includes a mixing tip which is detachable after the tip is locked to the syringe body, so that the tip may be replaced by a locking cap. Locking occurs when a neck extending from the body between two shoulders is inserted into a bore in the tip (or, alternatively, the cap) and the tip is rotated so that two symmetrically opposed tabs attached to the tip are each received within a recess determined by a shoulder and a locking rib attached to the shoulder, and two diametrically opposed detents extending from the neck are each received within a recess in the bore surface.

대표청구항 ▼

A double-barreled syringe is provided which includes a mixing tip which is detachable after the tip is locked to the syringe body, so that the tip may be replaced by a locking cap. Locking occurs when a neck extending from the body between two shoulders is inserted into a bore in the tip (or, altern

A double-barreled syringe is provided which includes a mixing tip which is detachable after the tip is locked to the syringe body, so that the tip may be replaced by a locking cap. Locking occurs when a neck extending from the body between two shoulders is inserted into a bore in the tip (or, alternatively, the cap) and the tip is rotated so that two symmetrically opposed tabs attached to the tip are each received within a recess determined by a shoulder and a locking rib attached to the shoulder, and two diametrically opposed detents extending from the neck are each received within a recess in the bore surface. er circuit. The buffer circuit further includes a delivery circuit for delivering an inhibit signal having a predetermined duration when the logic signal has a trailing edge and/or leading edge, and an inhibit circuit for inhibiting the transfer circuit and for isolating the output of the buffer circuit from the input of the buffer circuit when the inhibit signal is delivered. A storage circuit holds a logic value of the logic signal at the output of the buffer circuit when the inhibit signal is delivered. e prescribed value. 11. The method of claim 9, wherein the prescribed value is a ratio of the synchronizing signal width to the horizontal line width according to a VESA standard. 12. The method of claim 9, wherein the synchronizing signal width is set to the synchronizing signal width minus the horizontal line width if the synchronizing signal width is greater than the horizontal line width divided by 2. 13. The method of claim 9, wherein the synchronizing signal is a horizontal synchronizing signal. 14. An improved image display device having a signal processor, a microcomputer, a clock generator, and a scaler, the improvement comprising: a first counting circuit, coupled to receive a first clock signal and a synchronization signal, the synchronization signal being one of a horizontal synchronizing signal and a complex synchronizing signal; a reset generator, coupled to receive the first clock signal and the synchronization signal, and output a reset signal; a second counting circuit coupled to receive the first clock signal and the reset signal, wherein the first counting circuit counts a width of the synchronizing signal, and the second counting circuit counts a horizontal line width. 15. The apparatus claim 14, wherein the first counting circuit comprises a first counter coupled to a first register, the second counting circuit comprises a second counter coupled to a second register, the first register receives an output of the first counter and a second clock signal output from the reset generator, and the second register receives an output of the second counter and a second clock signal. 16. The apparatus of claim 15, further comprising: a synchronizing signal processor, coupled to receive a plurality of synchronization signals and output a vertical synchronization signal and one of the horizontal synchronization signal and the complex synchronization signal; a microcomputer coupled to receive the output of the synchronizing signal processor and the first and second registers; a clock generator to generate the first clock signal; and a scaler; coupled to receive an R/G/B image signal, the first clock signal, and the horizontal synchronizing signal. 17. The apparatus of claim 14, wherein the reset signal generator comprises: a first latch, coupled to receive the first clock signal and one of the horizontal synchronizing signal and complex synchronizing signal; a second latch, coupled to receive the output of the first latch; a logic gate, coupled to receive and logically combine the output of the first latch as a first input and the second latch as a second input to generate the second clock signal. 18. The apparatus of claim 17, further comprising a first inverter, coupled to receive the output of the first latch and provide the first input to the logic gate, and a second inverter coupled to receive the second clock signal to generate the reset signal. 19. A method for detecting an abnormal synchronizing signal, comprising: detecting a width of a synchronizing signal, the synchronizing signal being one of a horizontal synchronizing signal and a complex synchronizing signal; detecting a width of a corresponding horizontal line; determining whether the width of the synchronizing signal is smaller than half of the width of the horizontal line; if the width of the synchronization signal is smaller than half of the width of the horizontal line, then determining if a ratio of the synchronizing signal width to the horizontal line width is greater than a prescribed value; and if it is determined that the synchronizing signal width is not smaller than half of the horizontal line width, then setting a revised synchronizing signal width equivalent to the synchronizing signal width minus the horizontal line width, and determining if a ratio of the revised synchronizing signal width to the horizontal line width is greater than or equal to the prescribed value. 20. The method of claim 19, wherein the pre