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The present semiconductor element comprises a semiconductor substrate, a wiring pad formed thereon, a layer of barrier metal formed thereon, an intermetallic compound Ag3Sn formed thereon, and a protruded electrode consisting of low-melting metal formed thereon. In addition, a fabricating method of

The present semiconductor element comprises a semiconductor substrate, a wiring pad formed thereon, a layer of barrier metal formed thereon, an intermetallic compound Ag3Sn formed thereon, and a protruded electrode consisting of low-melting metal formed thereon. In addition, a fabricating method of a semiconductor element comprises the steps of forming a wiring pad on a semiconductor substrate, forming a layer of barrier metal thereon, forming a metallic layer containing Ag thereon, forming a layer of low-melting metal containing Sn thereon, and melting the layer of low-melting metal containing Sn to form a protruded electrode and simultaneously to form an intermetallic compound Ag3Sn at an interface between the metallic layer containing Ag and the layer of low-melting metal containing Sn. Thus, with Pb-free solder, a semiconductor element of high reliability can be obtained.

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The present semiconductor element comprises a semiconductor substrate, a wiring pad formed thereon, a layer of barrier metal formed thereon, an intermetallic compound Ag3Sn formed thereon, and a protruded electrode consisting of low-melting metal formed thereon. In addition, a fabricating method of

The present semiconductor element comprises a semiconductor substrate, a wiring pad formed thereon, a layer of barrier metal formed thereon, an intermetallic compound Ag3Sn formed thereon, and a protruded electrode consisting of low-melting metal formed thereon. In addition, a fabricating method of a semiconductor element comprises the steps of forming a wiring pad on a semiconductor substrate, forming a layer of barrier metal thereon, forming a metallic layer containing Ag thereon, forming a layer of low-melting metal containing Sn thereon, and melting the layer of low-melting metal containing Sn to form a protruded electrode and simultaneously to form an intermetallic compound Ag3Sn at an interface between the metallic layer containing Ag and the layer of low-melting metal containing Sn. Thus, with Pb-free solder, a semiconductor element of high reliability can be obtained. The method of fabricating a transistor in a semiconductor device according to claim 2, wherein the sacrificial layer is formed of photoresist material. 4. The method of claim 2, wherein the etch mask is formed by forming a nitride layer on the semiconductor substrate and then by patterning the nitride layer by photolithography. 5. The method of claim 4, further comprising the step of forming a buffer layer between the nitride layer and the semiconductor substrate. 6. The method of claim 2, wherein the step of forming the device isolation layer further comprises: forming an oxide layer on the etch mask wherein the oxide layer is formed to a thickness enabling to filling up the first and second trenches sufficiently; and exposing an inner surface of the second trench by removing the oxide layer in the second trench. 7. The method of claim 1, further comprising the step of forming a silicide layer on the impurity diffusion regions. 8. The method of claim 1, the step of forming the impurity diffusion regions further comprising: forming an ion-buried layer in the active area of the semiconductor substrate except the first trench by ion implantation with impurity ions of the second conductive type; and diffusing the impurity ions in the ion-buried layer. 9. The method of claim 1, the step of filling up the second trench with a conductive substance further comprising the step of forming an insulating layer on an exposed surface of the conductive substance. 10. A method of fabricating a transistor in a semiconductor device, comprising: forming a first etch mask on a predetermined portion of a first conductivity type semiconductor substrate in which an active area and a device isolation area are defined wherein a gate forming area is defined in the active area and wherein the first etch mask is formed to expose the device isolation area; increasing an etch rate of the exposed device isolation area of the substrate by ion implantation; forming a second etch mask exposing the gate forming area of the semiconductor substrate additionally by removing a portion of the first etch mask; forming a first trench and a second trench simultaneously by removing portions of the substrate exposed by the second etch mask wherein the first trench has a first depth and the second trench has a second depth, less than the first depth, to define the device isolation area and the gate by; forming a device isolation layer by filling up the first trench with an insulator; forming a gate insulating layer on an inner surface of the second trench; forming a conductive layer on the second etch mask and device isolation layer including the second trench covered with the gate insulating layer; exposing tops of the device isolation layer and the second etch mask by carrying out chemical mechanical polishing on the conductive layer wherein a gate formed of a portion of the conductive layer remains only in the second trench; forming an additional insulating layer on an exposed surface of the gate; removing the second etch mask; and forming a pair of impurity diffusion regions of a second conductivity type respectively in the active area of the substrate between the first and second trenches without having formed an epitaxial layer. 11. The method of claim 10, wherein the etch mask is formed by forming a nitride layer on the semiconductor substrate and then by patterning the nitride layer by photolithography. 12. The method of claim 10, wherein the method further comprising the step of forming a buffer layer for releasing a stress between the nitride layer and the semiconductor substrate. 13. The method of claim 10, wherein the method further comprising the step of forming a silicide layer on the impurity diffusion regions. 14. The method of claim 10, wherein the step of forming the impurity diffusion regions further comprising: forming an ion-buried layer in the active area of the semiconductor substrate except the first trench by ion imp lantation with impurity ions of the second conductivity type; and diffusing the impurity ions in the ion-buried layer. 15. The method of claim 10, wherein the step of exposing portions of the device isolation layer and the second etch mask is performed by carrying out chemical mechanical polishing on the conductive layer, wherein a gate formed of a portion of the conductive layer remaining only in the second trench further comprising: forming a photoresist pattern only covering over the first trench on the conductive layer; leaving a portion of the conductive layer on the gate insulating layer in the second trench by removing portions of the conductive layer not covered with the photoresist pattern; removing the photoresist pattern; and forming a gate by removing portions of the remaining conductive layer, the device isolation layer, and the gate insulating layer to expose a portion of the second etch mask by planarization, wherein the gate is formed of the remaining conductive layer. 16. A method of forming a semiconductor transistor comprising: forming isolation regions in a substrate at a first depth; forming a gate electrode in the substrate between the isolation regions at a second depth at the same time said isolation regions are formed at said first depth, without having formed an epitaxial layer; and forming a source and a drain between the isolation regions and the gate electrode. 17. A method of forming a semiconductor transistor comprising: forming a pair of first trenches in a non-active region of a substrate; forming a second trench in an active region of the substrate at the same time said pair of first trenches are formed; forming a source region and a drain region adjacent each first trench; and forming a gate region in the second trench, the gate region electrically connecting the source region with the drain region, without having formed an epitaxial layer. 18. A method of forming a semiconductor transistor, comprising: forming a first trench in a substrate; forming a second trench in the substrate opposing the first trench, at the same time the first trench is formed; forming a third trench between the first and second trenches, at the same time the first and second trenches are formed, said third trench having a depth that is less than a depth of the first and second trenches; forming a source between the first trench and the third trench; forming a drain between the second trench and the third trench; and forming a gate in the third trench, the gate electrically controlling a semiconductor channel formed between the source and the drain without having formed an epitaxial layer. 19. The method of claim 18, wherein the first and second trenches are formed by etching at a first rate. 20. The method of claim 19, wherein the third trench is formed by etching at a second rate. 21. The method of claim 20, wherein the first rate and the second rate are different. 22. The method of claim 21, wherein the first rate is greater than the second rate. 23. The method of claim 19, wherein the method does not require formation of a mono-crystalline layer. ethod for blanket ion implanting a semiconductor substrate surface to induce uniform damage over desired portions of the surface thereby reducing non-uniform etch effects caused by the varying etch rates of surface materials and conditions during surface cleaning. The invention includes providing a semiconductor substrate having gate oxide regions and a sacrificial oxide layer of a predetermined thickness formed thereon. The surface of the substrate is pattern masked to reveal openings in the gate oxide regions and ion implanted through the openings in the pattern mask to form gate oxide regions. The pattern mask is removed from the substrate and a blanket implantation of the sacrificial oxide layer is performed. The substrate is then cleaned to remove the sacrificial oxide layer leaving the substrate in readiness for further processing.