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Fully programmable I/O pin with memory 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03K-019/173
출원번호 US-0187545 (1998-11-05)
발명자 / 주소
  • Cheung, Sammy S. Y.
  • Rangasayee, Krishna
출원인 / 주소
  • Altera Corporation
대리인 / 주소
    Beyer Weaver & Thomas LLP
인용정보 피인용 횟수 : 70  인용 특허 : 9

초록

The present invention provides a programmable pin that may be selectively configured to operate as a signal pin or a power pin. A programmable pin provides increased flexibility in the design of integrated circuit devices. Programmable pins may also be used to provide better performance of the entir

대표청구항

The present invention provides a programmable pin that may be selectively configured to operate as a signal pin or a power pin. A programmable pin provides increased flexibility in the design of integrated circuit devices. Programmable pins may also be used to provide better performance of the entir

이 특허에 인용된 특허 (9)

  1. Oba Kaori,JPX, Bus driver failure detection system.
  2. Freidin Philip (Sunnyvale CA), Flexible, reconfigurable terminal pin.
  3. Sample Stephen P. ; Butts Michael R. ; Norman Kevin A. ; Patel Rakesh H., I/O buffer circuit with pin multiplexing.
  4. Morris Bernard Lee ; Patel Bijit Thakorbhai, Low power, high voltage-tolerant bus holder circuit in low voltage technology.
  5. Cliff Richard G. ; Reddy Srinivas T. ; Jefferson David E. ; Raman Rina ; Cope L. Todd ; Lane Christopher F. ; Huang Joseph ; Heile Francis B. ; Pedersen Bruce B. ; Mendel David W. ; Lytle Craig S. ; , Programmable logic array intergrated circuit devices.
  6. Tang Dandas K. (Tempe AZ) Sutton Timothy W. (Mesa AZ), Programmable pin for use in programmable logic devices.
  7. Whetsel Lee D. (Plano TX), Scan cell output latches using switches and bus holders.
  8. Pang Jianhua (Arlington TX), Serial interface having control circuits for enabling or disabling N-channel or P-channel transistors to allow for opera.
  9. Josephson Gregg R. (Aloha OR) Shen Ju (San Jose CA) Darling Roy D. (Forest Grove OR) Cheng Chan-Chi J. (San Jose CA), Structure and method for multiplexing pins for in-system programming.

이 특허를 인용한 특허 (70)

  1. Pitkethly, Scott; Masleid, Robert Paul, Advanced repeater utilizing signal distribution delay.
  2. Pitkethly, Scott, Advanced repeater with duty cycle adjustment.
  3. Pitkethly, Scott, Advanced repeater with duty cycle adjustment.
  4. Pitkethly, Scott, Advanced repeater with duty cycle adjustment.
  5. Low, Chia How, Apparatuses, methods, and systems for providing a dynamic bias voltage to one or more transistors of a transceiver.
  6. Caty, Olivier; Schöber, Volker, Bus signal hold cell, bus system, and method.
  7. Masleid, Robert Paul; Dholabhai, Vatsal, Circuit with enhanced mode and normal mode.
  8. Masleid, Robert Paul; Kowalczyk, Andre, Circuits and methods for detecting and assisting wire transitions.
  9. Masleid, Robert, Circuits, systems and methods relating to a dynamic dual domino ring oscillator.
  10. Masleid, Robert Paul, Column select multiplexer circuit for a domino random access memory array.
  11. Masleid, Robert Paul, Configurable delay chain with stacked inverter delay elements.
  12. Dybsetter,Gerald L.; Hahin,Jayne C., Configurable input/output terminals.
  13. Kutz, Harold; Williams, Timothy; Sullam, Bert; Metzler, Robert W.; Nemecek, Craig; Blom, Eric; Richmond, Melany; Snyder, Warren; Wright, David G.; Erickson, Jeffrey; Verge, Greg, Configurable reset pin for input/output port.
  14. Masleid, Robert Paul, Configurable tapered delay chain with multiple sizes of delay elements.
  15. Masleid, Robert P.; Pitkethly, Scott, Cross point switch.
  16. Masleid, Robert P.; Pitkethly, Scott, Cross point switch.
  17. Masleid, Robert P.; Pitkethly, Scott, Cross point switch.
  18. Masleid, Robert P, Dynamic ring oscillators.
  19. Rabinovitch, Alexander; Guerin, Xavier, Efficient resolution of latch race conditions in emulation.
  20. Vaduvatha, Srinivas; Venkataraman, Srinivas; Gupta, Anurag P.; Garapally, Praveen; Bristol, Norman; Sen, Dibyendu, Flexible pin allocation.
  21. Vaduvatha, Srinivas; Venkataraman, Srinivas; Gupta, Anurag P.; Garapally, Praveen; Bristol, Norman; Sen, Dibyendu, Flexible pin allocation.
  22. Lee, Eng H; Loo, Kok W, I/O circuitry for reducing ground bounce and VCC sag in integrated circuit devices.
  23. Chambers, Peter, Input/output circuit for handling unconnected I/O pads.
  24. Chambers,Peter, Input/output circuit for handling unconnected I/O pads.
  25. Rogers,J. Clark; Kris,Bryan, Integrated circuit device having at least one of a plurality of bond pads with a selectable plurality of input-output functionalities.
  26. Wright, David G., Integrity checking of configurable data of programmable device.
  27. Wright, David G., Integrity checking of configuration data of programmable device.
  28. Wright, David G., Intelligent power supervisor.
  29. Wright, David G., Intelligent power supervisor.
  30. Wright, David G., Intelligent power supervisor.
  31. Wright, David G., Intelligent voltage regulator.
  32. Wright, David G., Intelligent voltage regulator.
  33. Wright, David G., Intelligent voltage regulator.
  34. Wright, David G., Intelligent voltage regulator.
  35. Wright, David G., Interface circuit and method for programming or communicating with an integrated circuit via a power supply pin.
  36. Wright, David G., Interrupt latency reduction.
  37. Wright, David G., Interrupt latency reduction.
  38. Masleid, Robert P, Inverting zipper repeater circuit.
  39. Masleid, Robert P., Inverting zipper repeater circuit.
  40. Masleid, Robert Paul, Inverting zipper repeater circuit.
  41. Masleid, Robert, Leakage efficient anti-glitch filter.
  42. Bhunia,Swarup; Mahmoodi,Hamid; Raychowhury,Arijit; Mukhopadhyay,Saibal; Roy,Kaushik, Low power scan design and delay fault testing technique using first level supply gating.
  43. Miura, Seiji; Haraguchi, Yoshinori; Abe, Kazuhiko; Kaneko, Shoji; Yabu, Akira, Memory device with pin register to set input/output direction and bitwidth of data signals.
  44. Richman, Russell Mark, Method and system for wireless communication among integrated circuits within an enclosure.
  45. Rigge, Lawrence Allen, Method and system for wireless communication with an integrated circuit under evaluation.
  46. Cordan, Ernest; Hunter, Robert; Cornwall, Michael, One pin calibration assembly and method for sensors.
  47. Nguyen,Nam Duc, Phase detector for RZ.
  48. Masleid, Robert Paul, Power efficient multiplexer.
  49. Masleid, Robert Paul, Power efficient multiplexer.
  50. Masleid, Robert Paul, Power efficient multiplexer.
  51. Masleid, Robert Paul, Power efficient multiplexer.
  52. Lewis,David, Programmable logic device latch circuits.
  53. Wright, David G., Programmable power supervisor.
  54. Wright, David G., Programmable power supervisor.
  55. Wright, David G., Programmable power supervisor.
  56. Wright, David G., Programmable voltage regulator.
  57. Rangan, Gopinath; Sung, Chiakang; Wang, Xiaobao; Pan, Philip; Chong, Yan; Kim, In Whan; Nguyen, Khai; Wang, Bonnie; Chang, Tzung-Chin; Huang, Joseph, Programmable, staged, bus hold and weak pull-up for bi-directional I/O.
  58. Masleid, Robert Paul; Dholabhai, Vatsal; Klingner, Christian, Repeater circuit having different operating and reset voltage ranges, and methods thereof.
  59. Masleid, Robert Paul; Dholabhai, Vatsal, Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability.
  60. Stoiber, Steven T.; Siu, Stuart, Ring based impedance control of an output driver.
  61. Stoiber, Steven T.; Siu, Stuart, Ring based impedance control of an output driver.
  62. Masleid, Robert Paul; Sousa, Jose; Kottapalli, Venkata, Scannable dynamic circuit latch.
  63. Shahparnia, Shahrooz; Krah, Christoph H., Self capacitance touch sensing.
  64. Sumita, Masaya, Semiconductor device.
  65. Sumita, Masaya, Semiconductor device.
  66. Bae, Chang Hyun; Heo, Nak won, Semiconductor memory device with strengthened power and method of strengthening power of the same.
  67. Masleid, Robert P.; Burr, James B., Stacked inverter delay chain.
  68. Pitkethly, Scott; Masleid, Robert P., Triple latch flip flop system and method.
  69. Pitkethly,Scott; Masleid,Robert P., Triple latch flip flop system and method.
  70. Wright, David G., Ultra low power sleep mode.
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