One cell programmable switch using non-volatile cell with unidirectional and bidirectional states
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H03K-019/177
G11C-016/04
출원번호
US-0873153
(2001-06-01)
발명자
/ 주소
Sun, Albert
Sheu, Eric
Lo, Ying-Che
출원인 / 주소
Macronix International Co., Ltd.
대리인 / 주소
Haynes, Mark A.Haynes Beffel & Wolfeld LLP
인용정보
피인용 횟수 :
6인용 특허 :
41
초록▼
A one transistor, non-volatile programmable switch includes uni-directional and in some embodiments, bi-directional, states. The programmable switch is used in an integrated circuit, and comprises a first node and a second node coupled with corresponding circuit elements in the integrated circuit. A
A one transistor, non-volatile programmable switch includes uni-directional and in some embodiments, bi-directional, states. The programmable switch is used in an integrated circuit, and comprises a first node and a second node coupled with corresponding circuit elements in the integrated circuit. A non-volatile programmable transistor having a drain coupled to one of the first node and second node, a source coupled to the other of the first node and second node, gate coupled to an energizing conductor, and a data storage structure constitute the programmable switch. The non-volatile programmable transistor used in the switch is a charge programmable device (e.g. SONOS cell), in which the data storage structure comprises a nitride layer, or other charge trapping layer, between oxides or other insulators. The transistor stores four states, including a first unidirectional state in which the cell allows signal flow in a first direction, as second unidirectional state in which the cell allows signal flow in a second direction, opposite to the first direction, a third state in which the cell allows bi-directional signal flow, and a fourth state in which signal flow is blocked (the switch is open). A charge pump is coupled to the energizing conductor to produce a boosted voltage during logical operation of integrated circuit, so that voltage dissipation across the programmable switch is minimized or eliminated. In an embodiment, in which a charge programmable device is used, programmable circuitry is coupled to the first and second nodes, and to the energizing conductor to apply voltages sufficient to inject and remove charge from the charge storage structure for programming the charge programmable device. For integrated circuits in which voltages used for programming and erasing the non-volatile charge programmable device are high relative to the design rule for the circuit elements to be interconnected, a structure to withstand the high voltages is included.
대표청구항▼
A one transistor, non-volatile programmable switch includes uni-directional and in some embodiments, bi-directional, states. The programmable switch is used in an integrated circuit, and comprises a first node and a second node coupled with corresponding circuit elements in the integrated circuit. A
A one transistor, non-volatile programmable switch includes uni-directional and in some embodiments, bi-directional, states. The programmable switch is used in an integrated circuit, and comprises a first node and a second node coupled with corresponding circuit elements in the integrated circuit. A non-volatile programmable transistor having a drain coupled to one of the first node and second node, a source coupled to the other of the first node and second node, gate coupled to an energizing conductor, and a data storage structure constitute the programmable switch. The non-volatile programmable transistor used in the switch is a charge programmable device (e.g. SONOS cell), in which the data storage structure comprises a nitride layer, or other charge trapping layer, between oxides or other insulators. The transistor stores four states, including a first unidirectional state in which the cell allows signal flow in a first direction, as second unidirectional state in which the cell allows signal flow in a second direction, opposite to the first direction, a third state in which the cell allows bi-directional signal flow, and a fourth state in which signal flow is blocked (the switch is open). A charge pump is coupled to the energizing conductor to produce a boosted voltage during logical operation of integrated circuit, so that voltage dissipation across the programmable switch is minimized or eliminated. In an embodiment, in which a charge programmable device is used, programmable circuitry is coupled to the first and second nodes, and to the energizing conductor to apply voltages sufficient to inject and remove charge from the charge storage structure for programming the charge programmable device. For integrated circuits in which voltages used for programming and erasing the non-volatile charge programmable device are high relative to the design rule for the circuit elements to be interconnected, a structure to withstand the high voltages is included. , and on said bit patterns, and (i) a setting means of, when said mode is D mode, setting a second subset of said output channels, disjoint from said first subset of output channels, based on a subset of said plurality of input channels, and on said bit patterns, whereby said programmable logic device can set certain output channels by using said storage memory as a lookup table, and can set certain other output channels by bypassing said storage memory and directly using certain inputs to set said other output channel values. 2. The programmable logic device of claim 1, wherein said bit patterns correspond to one or more logic equations, each of which pass data, unchanged, from an input to an output. 3. The programmable logic device of claim 2, wherein said means of setting a first subset of said output channels comprises setting said outputs to the values of said selected bits from said storage device, and where said means of setting a second subset of said output channels comprises, for each of said logic equations, a switching means for connecting the output channel corresponding to said output specified by said logic equation to the input channel corresponding to said input specified by said logic equation when said bit pattern corresponding to said logic equation has been detected, and where said switching means will otherwise set said output channel to one of said values of said selected bits, whereby certain outputs may be generated using the device's internal lookup table, while other outputs are directly connected to certain inputs. 4. The programmable logic device of claim 3, wherein said switching means comprises a pair of pass transistors, said pass transistors having their outputs connected together, said connection forming a common pole, said transistors having their gates driven by complimentary select signals, said transistors further each having their input available as a pole, whereby said pair of pass transistors thereby acts as a single pole double throw switch, electronically controllable by said select signals. 5. The programmable logic device of claim 3, wherein said switching means comprises a mechanical relay, acting as a single pole double throw switch. 6. The programmable logic device of claim 1, wherein said bit patterns correspond to all possible logic equations for passing data, unchanged, from an input to an output. 7. A programmable logic device, operating in one of two modes, one of said modes being called C mode, the other of said modes being called D mode, said device comprising: (a) a plurality of input channels, (b) a mode selection means of choosing C or D mode based on a subset of said plurality of input channels, (c) a plurality of output channels, (d) an internal storage memory, viewed conceptually as a lookup table organized in rows and columns, the number of said rows being 2 raised to the power of the number of said input channels/2, the number of said columns being the same as the number of said output channels, (e) a writing means of modifying the contents of said storage memory based on said mode and a subset of said plurality of input channels, (f) a reading means of selecting some set of bits from said storage memory based on said mode and on the values of a set of internal inputs, (g) an input disconnect means of, when said mode is D mode, selectively connecting or disconnecting each input of a subset of said plurality of input channels from said means of selecting some set of bits, based on a plurality of input disconnect signals, corresponding one-to-one with said subset of said plurality of input channels, (h) a detecting means of detecting certain bit patterns in said storage memory, (i) a means of detecting certain lookup table properties of said lookup table, (j) a setting means of setting a first subset of said output channels based on said mode, on said set of bits, on said lookup table properties, and on said bit patterns, and (k) a setting means of, when said mode is D mode, setting a second subset of said output channels, disjoint from said first subset of output channels, based on said mode, on a subset of said plurality of input channels, on said lookup table properties, and on said bit patterns, whereby said programmable logic device can set certain output channels by using said storage memory as a lookup table, and can set certain other output channels by bypassing said storage memory and directly using certain inputs to set said other output channel values, and may further cause certain inputs to be disconnected from said internal storage memory lookup logic. 8. The programmable logic device of claim 7, wherein said bit patterns correspond to one or more logic equations, each of which pass data, unchanged, from an input to an output. 9. The programmable logic device of claim 7, wherein said bit patterns correspond to all possible logic equations for passing data, unchanged, from an input to an output. 10. The programmable logic device of claim 8, wherein said means of setting a first subset of said output channels comprises setting said outputs to the values of said selected bits from said storage device, and where said means of setting a second subset of said output channels comprises, for each of said logic equations, a bypass switching means for connecting the output channel corresponding to said output specified by said logic equation to the input channel corresponding to said input specified by said logic equation when said bit pattern corresponding to said logic equation has been detected, this state of said switching means being called "on," and where said switching means will otherwise set said output channel to one of said values of said selected bits, this state of said switching means being called "off," whereby certain outputs may be generated using the device's internal lookup table, while other outputs are directly connected to certain inputs. 11. The programmable logic device of claim 10, wherein said switching means comprises a pair of pass transistors, said pass transistors having their outputs connected together, said connection forming a common pole, said transistors having their gates driven by complimentary select signals, said transistors further each having their input available as a pole, whereby said pair of pass transistors thereby acts as a single pole double throw switch, electronically controllable by said select signals. 12. The programmable logic device of claim 10, wherein said switching means comprises a mechanical relay, acting as a single pole double throw switch. 13. The programmable logic device of claim 10, wherein said input disconnect means comprises a pass transistor. 14. The programmable logic device of claim 10, wherein said input disconnect means comprises a mechanical relay, acting as a single pole single throw switch. 15. The programmable logic device of claim 10, further including logic circuitry to cause each of said input disconnect signals to be set to "disconnect" when: (a) said input signal from said subset of said plurality of input channels corresponds to said input specified by said logic equation, (b) said properties of said lookup table include the property that exactly one of said columns of said lookup table contains any non-zero entries, and (c) said property has been detected, and to be set to "connect" otherwise, whereby inputs that are directly connected to outputs are also disconnected from the device's internal lookup table processing logic. 16. The programmable logic device of claim 10, further including logic circuitry to cause each of said input disconnect signals to be set to "disconnect" when: (a) said input signal from said subset of said plurality of input channels corresponds to said input specified by said logic equation, (b) said properties of said lookup table include the property that all of said columns of said lookup table which contain non-zero entries correspond to one of said outputs specified by said logic equations, and (c) said property has been detected, and to be set to "connect" otherwise, whereby inputs that are directly connected to outputs are also disconnected from the device's internal lookup table processing logic if all other outputs are always 0. 17. The programmable logic device of claim 10, further including logic circuitry to cause each of said input disconnect signals to be set to "disconnect" when: (a) said input signal from said subset of said plurality of input channels corresponds to said input specified by said logic equation, (b) said properties of said lookup table include the property that said means of selecting some set of bits from said storage memory based on said mode and on the values of a set of inputs will, when said mode is D mode, for any combination of values of said inputs exclusive of all inputs corresponding to said inputs specified by said logic equations, select the same bits for all possible values of said inputs corresponding to said inputs specified by said logic equations, and (c) said property has been detected, and to be set to "connect" otherwise, whereby said input disconnect means will disconnect an input only if its value is not necessary to determine any outputs other than outputs which may be directly connected to inputs. 18. The programmable device of claim 10, further including a delay means so said switching means changes to the "on" state prior to said input disconnect signal being changed to "disconnect," and said switching means changes to the "off" state subsequent to said input disconnect signal being changed to "connect." etermined voltage. 16. The method of claim 12 further comprising electrically connecting the charge-emitting device to an object, and wherein the determined electrical potential difference corresponds to an electrical potential difference of the object with respect to the environment. 17. The method of claim 12 further comprising configuring a geometry of the gate with respect to a geometry of the emitter to facilitate the determination of the electrical potential difference between the charge-emitting device and the environment. 18. The method of claim 17 wherein the configured geometries of the gate and emitter induce at least a predetermined amount of current to flow to the gate. 19. A method for sensing and controlling an electrical potential difference of a space object with respect to an environment of the space object, comprising: electrically connecting an at least two-terminal charge-emitting device to an external surface of the space object; applying a voltage across two terminals of the charge-emitting device to induce charge obtained from the space object to flow from one of the terminals into the environment of the space object; measuring an electrical potential difference between the charge-emitting device and the environment of the space object based on currents that are measured in response to the applied voltage; and altering the flow of the charge from the emitting terminal by adjusting the applied voltage, to control the electrical potential difference between the space object and the environment of the space object. 20. A sensor for measuring an electrical potential difference, comprising: a charge-emitting device
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