IPC분류정보
| 국가/구분 |
United States(US) Patent
등록
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| 국제특허분류(IPC7판) |
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| 출원번호 |
US-0220089
(1998-12-23)
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발명자
/ 주소 |
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| 출원인 / 주소 |
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| 대리인 / 주소 |
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| 인용정보 |
피인용 횟수 :
34 인용 특허 :
7 |
초록
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A method for transmitting data over a data bus with minimized digital control and data inter-symbol interference. The voltage level on the data bus is not permitted to reach the quiescent negated voltage level set by the bus terminator voltage. Additional time is provided for data detection circuitr
A method for transmitting data over a data bus with minimized digital control and data inter-symbol interference. The voltage level on the data bus is not permitted to reach the quiescent negated voltage level set by the bus terminator voltage. Additional time is provided for data detection circuitry to detect a first segment of data transferred over the data bus. A pause time is enabled after the data bus has been idle or paused for a prolonged period. After the first segment of data has been transferred, the method returns to normal operation by pausing for a normal period of time for data detection circuitry to detect subsequent segments of data transferred over the data bus. Additionally, during prolonged synchronous data transfers with unchanged data bits, the data bus is inverted and driven for further regulating the data bus voltage.
대표청구항
▼
A method for transmitting data over a data bus with minimized digital control and data inter-symbol interference. The voltage level on the data bus is not permitted to reach the quiescent negated voltage level set by the bus terminator voltage. Additional time is provided for data detection circuitr
A method for transmitting data over a data bus with minimized digital control and data inter-symbol interference. The voltage level on the data bus is not permitted to reach the quiescent negated voltage level set by the bus terminator voltage. Additional time is provided for data detection circuitry to detect a first segment of data transferred over the data bus. A pause time is enabled after the data bus has been idle or paused for a prolonged period. After the first segment of data has been transferred, the method returns to normal operation by pausing for a normal period of time for data detection circuitry to detect subsequent segments of data transferred over the data bus. Additionally, during prolonged synchronous data transfers with unchanged data bits, the data bus is inverted and driven for further regulating the data bus voltage. a measurement process, the interrogation surface would be pressed into contact with the non-uniform surface to cause individual ones of the interrogation devices to move, thereby causing the probe head to conform to the non-uniform surface. d output lines, and read selection MOSFETs connecting said read output lines and said read bit lines, wherein in the reading operation, read signals produced on said read bit lines in accordance with said plurality of reference voltages are sequentially transmitted through said read selection MOSFETs to said read output lines, and converted into read data of a plurality of bits corresponding to said information voltage. 10. A semiconductor memory device according to claim 1, wherein selection circuits for said write word lines and said read word lines are separately provided on both sides of the memory array in the extended direction, and said write input lines, said write selection MOSFETs, and said read output lines, said read selection MOSFETs given for said write bit lines and said read bit lines are separately provided on both sides of the memory array in the extended direction. 11. A semiconductor memory device comprising: a plurality of memory cells each having a MOSFET for holding an information voltage of three or more values at its gate, a writing transistor for applying said information voltage of three or more values to said gate of said MOSFET, and a reading transistor connected in series with said MOSFET; a plurality of write word lines for controlling said writing transistors in a switching manner in accordance with an address signal; a plurality of read word lines for controlling said reading transistors in a switching manner in accordance with an address signal; a plurality of write bit lines arranged in the direction perpendicular to said write word lines, and to which said information voltage is transmitted; and a plurality of read bit lines arranged in the direction perpendicular to said read word lines and to which a source voltage of said MOSFET is transmitted through said reading transistor, wherein a read voltage corresponding to the source voltage of said MOSFET is converted into a digital signal, wherein said reading transistor is formed of a MOSFET, and said writing translator Is formed of a barrier-insulating film structure including a PLED transistor. 12. A semiconductor memory device according to claim 11, wherein said writing transistor having said barrier-insulating film structure including said PLED transistor is built up on the gate electrode of said MOSFET to have a longitudinal current path extended to the surface of said gate electrode. 13. A semiconductor memory device according to claim 12, wherein the gate electrodes of said MOSFET and said MOSFET of said reading transistor are provided in parallel between a pair of source and drain diffusion layers. 14. A semiconductor memory device according to claim 11, wherein said information voltage is formed of four values, and 2 bits are stored in each memory cell. 15. A semiconductor memory device comprising: a plurality of memory cells each having a MOSFET for holding an information voltage of three or more values at its gate, a writing transistor for applying said information voltage of three or more values to said gate of said MOSFET, and a reading transistor connected in series with said MOSFET; a plurality of write word lines for controlling said writing transistors in a switching manner in accordance with an address signal; a plurality of read word lines for controlling said reading transistors in a switching manner in accordance with an address signal; a plurality of write bit lines arranged in the direction perpendicular to said write word lines, and to which said information voltage is transmitted; and a plurality of read bit tines arranged in the direction perpendicular to said read word lines and to which a source voltage of said MOSFET is transmitted through said reading transistor, wherein a read voltage corresponding to the source voltage of said MOSFET is converted into a digital signal, wherein in the writing operation, said write word lines and said read word lines are selected, and a write vo ltage is produced so that the voltage produced from the source of said MOSFET and said information voltage to be written are coincident with each other, and transmitted to the gate of said MOSFET. 16. A semiconductor memory device according to claim 15, wherein said write voltage is produced from a voltage comparator circuit having a non-inverting input terminal to which said information voltage to be written is applied, and an inverting input terminal to which the voltage from the source of said MOSFET is applied. 17. A semiconductor memory device according to claim 16, wherein said information voltage to be written that is supplied to the non-inverting input terminal of said voltage comparator circuit is produced from a digital/analog converter circuit, and the voltage produced from the source of said MOSFET is also applied to an analog/digital converter circuit that produces read data. An apparatus according to claim 1, wherein, when R is an effective radius of the secondary light source, a relation among R, d, f, F and V is satisfied such that 2dR/f=nV/F, where n is an integer.
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