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Pillar connections for semiconductor chips and method of manufacture 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • B23K-035/14
출원번호 US-0564382 (2000-04-27)
발명자 / 주소
  • Tung, Francisca
출원인 / 주소
  • Advanpack Solutions Pte. Ltd.
대리인 / 주소
    Saile, George O.Ackerman, Stephen B.
인용정보 피인용 횟수 : 311  인용 특허 : 13

초록

A flip chip interconnect system comprises and elongated pillar comprising two elongated portions, one portion including copper and another portion including solder. The portion including copper is in contact with the semiconductor chip and has a length preferably of more than 55 microns to reduce th

대표청구항

1. A semiconductor device comprising: a semiconductor chip, and a plurality of pillars connected to the chip, each of said pillars comprising at least two elongated portions, one portion including copper and another portion including solder, said portion including copper in contact with the semi

이 특허에 인용된 특허 (13)

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  13. Love David George ; Moresco Larry Louis ; Chou William Tai-Hua ; Horine David Albert ; Wong Connie Mak ; Beilin Solomon Isaac, Wire interconnect structures for connecting an integrated circuit to a substrate.

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  163. Haba, Belgacem, Microelectronic packages with dual or multiple-etched flip-chip connectors.
  164. Haba, Belgacem, Microelectronic packages with dual or multiple-etched flip-chip connectors.
  165. Haba, Belgacem, Microelectronic packages with nanoparticle joining.
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  169. Uzoh, Cyprian Emeka; Katkar, Rajesh, Multiple bond via arrays of different wire heights on a same substrate.
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  171. Haba, Belgacem; Co, Reynaldo; Saga Cizek, Rizza Lee; Zohni, Wael, Off substrate kinking of bond wire.
  172. Hsu, Chun-Lei; Chen, Yu-Feng; Ho, Ming-Che; Lu, De-Yuan; Liu, Chung-Shi, Package on package devices and methods of packaging semiconductor dies.
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  179. Chau, Ellis; Co, Reynaldo; Alatorre, Roseann; Damberg, Philip; Wang, Wei-Shun; Yang, Se Young; Zhao, Zhijun, Package-on-package assembly with wire bond vias.
  180. Sato, Hiroaki; Kang, Teck-Gyu; Haba, Belgacem; Osborn, Philip R.; Wang, Wei-Shun; Chau, Ellis; Mohammed, Ilyas; Masuda, Norihito; Sakuma, Kazuo; Hashimoto, Kiyoaki; Inetaro, Kurosawa; Kikuchi, Tomoyuki, Package-on-package assembly with wire bonds to encapsulation surface.
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  185. Prabhu, Ashok S.; Katkar, Rajesh, Packaged microelectronic device for a package-on-package device.
  186. Yu, Chen-Hua; Jeng, Shin-Puu; Hou, Shang-Yun; Hsu, Kuo-Ching; Hsieh, Cheng-Chieh; Shih, Ying-Ching; Tsai, Po-Hao; Huang, Cheng-Lin; Lin, Jing-Cheng, Packaging structures and methods with a metal pillar.
  187. Fan, Wen Jeng, Pillar-to-pillar flip-chip assembly.
  188. Haba, Belgacem; Mohammed, Ilyas, Pin attachment.
  189. Hwang, Chien Ling; Wu, Yi-Wen; Liu, Chung-Shi, Post passivation interconnect with oxidation prevention layer.
  190. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection process and structures.
  191. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection process and structures.
  192. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  193. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
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  199. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection schemes on top of the IC chips.
  200. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection schemes on top of the IC chips.
  201. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection structures.
  202. Lin, Mou-Shiung; Lee, Jin-Yuan; Lei, Ming-Ta; Huang, Ching-Cheng, Post passivation metal scheme for high-performance integrated circuit devices.
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  207. Liu, Chung-Shi; Hwang, Chien Ling; Ho, Ming-Che, Protection layer for preventing UBM layer from chemical attack and oxidation.
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  209. Mohammed, Ilyas, Reconstituted wafer-level package dram with conductive interconnects formed in encapsulant at periphery of the package.
  210. Huang, Ching-Cheng; Lin, Chuen-Jye; Lei, Ming-Ta; Lin, Mou-Shiung, Reliable metal bumps on top of I/O pads after removal of test probe marks.
  211. Hsiao, Ching-Wen; Chuang, Yao-Chun; Chen, Chen-Shien; Kuo, Chen-Cheng; Huang, Ru-Ying, Robust joint structure for flip-chip bonding.
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  217. Liu, Chung-Shi; Yu, Chen-Hua, Self-aligned protection layer for copper post structure.
  218. Liu, Chung-Shi; Yu, Chen-Hua, Self-aligned protection layer for copper post structure.
  219. Kang, Teck-Gyu; Wang, Wei-Shun; Sato, Hiroaki; Hashimoto, Kiyoaki; Nakadaira, Yoshikuni; Masuda, Norihito; Haba, Belgacem; Mohammed, Ilyas; Damberg, Philip, Semiconductor chip assembly and method for making same.
  220. Kang, Teck-Gyu; Wang, Wei-Shun; Sato, Hiroaki; Hashimoto, Kiyoaki; Nakadaira, Yoshikuni; Masuda, Norihito; Haba, Belgacem; Mohammed, Ilyas; Damberg, Philip, Semiconductor chip assembly and method for making same.
  221. Lo, Jian-Wen; Chen, Chien-Fan, Semiconductor device.
  222. Pendse, Rajendra D., Semiconductor device and method of forming bump-on-lead interconnection.
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  224. Shariff, Dzafir; Yam, Kwong Loon; Chia, Lai Yee; Hsiao, Yung Kuan, Semiconductor device and method of forming conductive pillar having an expanded base.
  225. Pendse, Rajendra D., Semiconductor device and method of forming electrical interconnect with stress relief void.
  226. Pendse, Rajendra D., Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate.
  227. Pendse, Rajendra D., Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask.
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  232. Lai, Yi-Jen; Han, Chih-Kang; Chan, Chien-Pin; Chien, Chih-Yuan; Yang, Huai-Tei, Semiconductor device and semiconductor assembly with lead-free solder.
  233. Lai, Yi-Jen; Han, Chih-Kang; Chan, Chien-Pin; Chien, Chih-Yuan; Yang, Huai-Tei, Semiconductor device and semiconductor assembly with lead-free solder.
  234. Sohn, Eun Sook; Kim, Jin Young; Hwang, Tae Kyung, Semiconductor device capable of preventing dielectric layer from cracking.
  235. Ke, Chun-Chi; Huang, Chien-Ping, Semiconductor device having conductive bumps and deviated solder pad.
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  237. Lotfi, Ashraf W.; Demski, Jeffrey; Feygenson, Anatoly; Lopata, Douglas Dean; Norton, Jay; Weld, John D., Semiconductor device including alternating source and drain regions, and respective source and drain metallic strips.
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  241. Tseng, Yu-Jen; Lin, Yen-Liang; Kuo, Tin-Hao; Chen, Chen-Shien; Lii, Mirng-Ji, Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices.
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  243. Liu, Chung-Shi; Yu, Chen-Hua, Semiconductor die contact structure and method.
  244. Liu, Chung-Shi; Yu, Chen-Hua, Semiconductor die contact structure and method.
  245. Cheng, Ming-Da; Lin, Chih-Wei; Huang, Kuei-Wei; Tsai, Yu-Peng; Lin, Chun-Cheng; Liu, Chung-Shi, Semiconductor package.
  246. Huang, Chien Ping; Wang, Yu-Po; Huang, Chih-Ming, Semiconductor package free of substrate and fabrication method thereof.
  247. Huang,Chien Ping; Wang,Yu Po; Huang,Chih Ming, Semiconductor package free of substrate and fabrication method thereof.
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  250. Wang, Sheng-Ming; Feng, Hsiang-Ming; Kuo, Yen-Hua, Semiconductor package substrates having layered circuit segments, and related methods.
  251. Chen, Tien-Szu; Chen, Kuang-Hsiung; Wang, Sheng-Ming; Feng, Hsiang-Ming; Kuo, Yen-Hua, Semiconductor package substrates having pillars and related methods.
  252. Shih, Meng-Kai; Lee, Chang-Chi, Semiconductor package with integrated metal pillars and manufacturing methods thereof.
  253. Haba, Belgacem; Co, Reynaldo; Saga Cizek, Rizza Lee; Zohni, Wael, Severing bond wire by kinking and twisting.
  254. Daubenspeck, Timothy H.; Gambino, Jeffrey P.; Misra, Ekta; Muzzy, Christopher D.; Sauter, Wolfgang; Scott, George J., Solder bump connections.
  255. Daubenspeck, Timothy H.; Gambino, Jeffrey P.; Misra, Ekta; Muzzy, Christopher D.; Sauter, Wolfgang; Scott, George J., Solder bump connections.
  256. Lin, Mou-Shiung, Solder interconnect on IC chip.
  257. Pendse, Rajendra D.; Kim, KyungOe; Kang, TaeWoo, Solder joint flip chip interconnection.
  258. Pendse, Rajendra D.; Kim, KyungOe; Kang, TaeWoo, Solder joint flip chip interconnection.
  259. Pendse, Rajendra D.; Kim, KyungOe; Kang, TaeWoo, Solder joint flip chip interconnection having relief structure.
  260. Wilson, Stuart E.; Green, Ronald; Crisp, Richard Dewitt; Humpston, Giles, Stack microelectronic assemblies.
  261. Haba, Belgacem, Stackable molded microelectronic packages.
  262. Haba, Belgacem, Stackable molded microelectronic packages.
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  274. Villavicencio, Grant; Lee, Sangil; Alatorre, Roseann; Delacruz, Javier A.; McGrath, Scott, Stiffened wires for offset BVA.
  275. Lin, Mou-Shiung; Lei, Ming-Ta; Lin, Chuen-Jye, Structure and manufacturing method of a chip scale package.
  276. Haba, Belgacem; Mohammed, Ilyas; Caskey, Terrence; Co, Reynaldo; Chau, Ellis, Structure for microelectronic packaging with bond elements to encapsulation surface.
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  278. Haba, Belgacem; Mohammed, Ilyas, Structure for microelectronic packaging with terminals on dielectric mass.
  279. Chou, Chiu-Ming; Lin, Mou-Shiung, Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures.
  280. Uzoh, Cyprian Emeka, Structures and methods for low temperature bonding using nanoparticles.
  281. Uzoh, Cyprian Emeka, Structures and methods for low temperature bonding using nanoparticles.
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  290. Mohammed, Ilyas, Substrate-less stackable package with wire-bond interconnect.
  291. Mohammed, Ilyas, Substrate-less stackable package with wire-bond interconnect.
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  304. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Top layers of metal for integrated circuits.
  305. Katkar, Rajesh; Vu, Tu Tam; Lee, Bongsub; Bang, Kyong-Mo; Li, Xuan; Huynh, Long; Guevara, Gabriel Z.; Agrawal, Akash; Subido, Willmar; Mirkarimi, Laura Wills, Wafer-level packaging using wire bond wires in place of a redistribution layer.
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