초록 ▼

An apparatus and method for strip casting of metals on at least one endless belt. The apparatus employs a tapered molding section that is large at the point of molten metal entry and tapers to a smaller thickness where a pair of pinch rolls apply a compressive force that sets the final thickness of

An apparatus and method for strip casting of metals on at least one endless belt. The apparatus employs a tapered molding section that is large at the point of molten metal entry and tapers to a smaller thickness where a pair of pinch rolls apply a compressive force that sets the final thickness of the cast strip.

대표청구항 ▼

An apparatus and method for strip casting of metals on at least one endless belt. The apparatus employs a tapered molding section that is large at the point of molten metal entry and tapers to a smaller thickness where a pair of pinch rolls apply a compressive force that sets the final thickness of

An apparatus and method for strip casting of metals on at least one endless belt. The apparatus employs a tapered molding section that is large at the point of molten metal entry and tapers to a smaller thickness where a pair of pinch rolls apply a compressive force that sets the final thickness of the cast strip. to the first unit memory circuits and each of the second unit memory circuits finds the minimum value by calculating the logical sum of prescribed bits in the maximum value and a stored value. 10. Frequency comparison circuit described in claim 5 further comprising an output circuit that finds frequency comparison signals from the difference in values of adjacent first unit memory circuits or second unit memory circuits. se n-channel metal oxide semiconductor (NMOS) transistors, each of said first and second load circuits comprising a p-channel metal oxide semiconductor (PMOS) transistor. 13. The logic gate as recited in claim 1 wherein said first and second computational blocks comprise p-channel metal oxide semiconductor (PMOS) transistors, each of said first and second load circuits comprising an n-channel metal oxide semiconductor (NMOS) transistor. 14. The logic gate as recited in claim 1 wherein said first and second computational blocks comprise one polarity of metal oxide semiconductor (MOS) transistor, each of said first and second load circuits comprising an identical polarity of MOS transistor and an inverter. 15. The logic gate as recited in claim 1 wherein each of said first and second computational blocks comprises at least one n-channel metal oxide semiconductor (MOS) and at least one p-channel metal oxide semiconductor (MOS) transistor. 16. The logic gate as recited in claim 1 wherein said first and second load circuits comprise elements selected from the group consisting of: p-channel metal oxide semiconductor (PNOS) transistors; n-channel metal oxide semiconductor (NMOS) transistors; PMOS transistors having inverters coupled thereto; NMOS transistors having inverters coupled thereto; and an NMOS transistor, a PMOS transistor and an inverter. 17. A method of performing a logic operation, comprising: receiving, in a first computational block, a first set of input binary digits presented at a first set of binary inputs of said first computational block, said first computational block having a first set of transistors for said first set of binary inputs and sized to represent specific discrete weights; receiving, in a second computational block, a second set of input binary digits presented at a second set of binary inputs of said second computational block, said second computational block having a second set of transistors for said second set of binary inputs and sized to represent specific discrete weights; developing an output binary digit that is a function of a weighted sum of said first set of input binary digits; developing a complementary output binary digit that is a function of a weighted sum of said second set of input binary digits; driving a first load circuit of a cross-coupled differential load with said complementary output binary digit, said first load circuit including a first load transistor sized to represent a threshold value Θ(M1); and driving a second load circuit of said cross-coupled differential load with said output binary digit, said second load circuit including a second load transistor sized to represent a threshold value Θ(M2), at least one of said first set of transistors being sized differently from a corresponding one of said second set of transistors if said first load transistor is sized substantially identical to said second load transistor, each of said first set of transistors being sized substantially identical to corresponding ones of said second set of transistors if said first load transistor is sized differently from said second load transistor. 18. The method as recited in claim 17 further comprising increasing a noise tolerance of said logic gate. 19. The method as recited in claim 17 wherein said developing said output binary digit and said developing said complementary output binary digit are performed without employing a timing signal. 20. The method as recited in claim 17 further comprising performing a first threshold function with said first load circuit and said first computational block. 21. The method as recited in claim 20 wherein said output binary digit is further a function of said first threshold function. 22. The method as recited in claim 17 further comprising performing a second threshold function with said second load circuit and said second computational block. 23. The method as recited in claim 22 wherein said complementary output binary digit