$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Multi-finger current ballasting ESD protection circuit and interleaved ballasting for ESD-sensitive circuits 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H02H-009/00
출원번호 US-0881422 (2001-06-14)
발명자 / 주소
  • Verhaege, Koen Gerard Maria
  • Mergens, Markus Paul Josef
  • Russ, Cornelius Christian
  • Armer, John
  • Jozwiak, Phillip Czeslaw
출원인 / 주소
  • Sarnoff Corporation, Sarnoff Europe
대리인 / 주소
    Burke, William J.
인용정보 피인용 횟수 : 38  인용 특허 : 47

초록

A multi-finger electro-static discharge (ESD) protection circuit has at least two first resistive channels defining input fingers. At least two field effect transistor (FET) channels, each having a drain and source are connected to corresponding ones of the at least two input fingers. The gate termi

대표청구항

A multi-finger electro-static discharge (ESD) protection circuit has at least two first resistive channels defining input fingers. At least two field effect transistor (FET) channels, each having a drain and source are connected to corresponding ones of the at least two input fingers. The gate termi

이 특허에 인용된 특허 (47)

  1. Ker Ming D. (Hsinchu TWX) Lee Chung Y. (Chung-Li TWX) Wu Chung Y. (Hsinchu TWX) Ko Joe (Hsin-chu TWX), CMOS ESD protection circuit with parasitic SCR structures.
  2. Ker Ming-Dou (Hsin-Chu TWX) Wu Chung-Yu (Hsin-Chu TWX) Cheng Tao (Kaohsiung Hsien TWX) Wu Chau-Neng (Kaohsiung Hsien TWX) Yu Ta-Lee (Hsin-Chu Hsien TWX), Capacitor-couple electrostatic discharge protection circuit.
  3. Saitoh Yutaka (Tokyo JPX) Osanai Jun (Tokyo JPX) Kojima Yoshikazu (Tokyo JPX) Ishii Kazutoshi (Tokyo JPX), Current regulating semiconductor integrated circuit device and fabrication method of the same.
  4. Kleveland Bendik ; Lee Thomas H., Distributed ESD protection device for high speed integrated circuits.
  5. Lin Shi-Tron,TWX ; Wong Shyh-Chyi,TWX, Dual-node capacitor coupled MOSFET for improving ESD performance.
  6. Lien Chuen-Der ; Wong Tak Kwong ; Yeh Tzong-Kwang, ESD damage protection using a clamp circuit.
  7. Li Sheau-Suey (Cupertino CA) Ong Randy T. (Cupertino CA) Broydo Samuel (Los Altos Hills CA) Duong Khue (San Jose CA), ESD protection circuit.
  8. Li Sheau-Suey (Cupertino CA) Ong Randy T. (Cupertino CA) Broydo Samuel (Los Altos Hills CA) Duong Khue (San Jose CA), ESD protection circuit.
  9. Avery Leslie R. (Flemington NJ), ESD protection circuit for integrated circuit.
  10. Lee Kowk Fai V. (Irvine CA) Lee Alan (Irvine CA), ESD protection circuit with segmented buffer transistor.
  11. Avery Leslie Ronald, ESD protection for overvoltage friendly input/output circuits.
  12. Watt Jeffrey T. (Mountain View CA), ESD protection structure for P-well technology.
  13. Diaz Carlos H. (Urbana IL) Duvvury Charvaka (Plano TX) Kang Sung-Mo (Champaign IL), ESD/EOS protection circuits for integrated circuits.
  14. Watt Jeffrey (Mountain View CA), Electrostatic discharge (ESD) protection structure for high voltage pins.
  15. Avery Leslie R. (Flemington NJ), Electrostatic discharge protection circuit for a NMOS or lateral NPN transistor.
  16. Mortensen Gordon L. (San Jose CA), Electrostatic discharge protection device and a method for simultaneously forming MOS devices with both lightly doped an.
  17. Miller William E. (Los Gatos CA), Electrostatic discharge protection for CMOS integrated circuits.
  18. Leach Jerald G. (Houston TX), Electrostatic discharge protection in integrated circuits, systems and methods.
  19. Lin Shi-Tron,TWX, Electrostatic discharge protection metal-oxide semiconductor field-effect transistor with segmented diffusion regions.
  20. Lee Jian-Hsing,TWX ; Wu Yi-Hsun,TWX ; Shih Jiaw-Ren,TWX ; Liu Jing-Meng,TWX, Electrostatic discharge protective circuit for reducing an undesired channel turn-on.
  21. Jeong Jae Goan,KRX, Electrostatic protection circuit in a semiconductor device.
  22. Hsu Chen-Chung,TWX ; Tang Tien-Hao,TWX, Field device electrostatic discharge protective circuit.
  23. Tihanyi Jen (Munich DEX), Field effect transistor.
  24. Krieger Gadi (Stanford CA) Eitan Boaz (Sunnyvale CA), Input circuit for protecting against damage caused by electrostatic discharge.
  25. Chang Ming-Chien,TWX, Input/output electrostatic discharge protection circuit for an integrated circuit (IC).
  26. Yamaguchi Yasuo,JPX ; Sato Hirotoshi,JPX ; Inoue Yasuo,JPX ; Iwamatsu Toshiaki,JPX, Input/output protection circuit having an SOI structure.
  27. Walker John D. (Colorado Springs CO) Gioia Samuel C. (Colorado Springs CO), Lightly doped drain ballast resistor.
  28. Kishi Shuuji,JPX, Method of fabricating electrostatic discharge device.
  29. Diaz Carlos H. (Urbana IL) Duvvury Charvaka (Plano TX) Kang Sung-Mo (Champaign IL), Method of placing source contacts for efficient ESD/EOS protection in grounded substrate MOS integrated circuit.
  30. Yu Ta-Lee,TWX ; Young Konrad,TWX, Multi-finger MOS transistor element.
  31. Huang Tiao-Yuan (Cupertino CA), Multi-finger input buffer with transistor gates capacitively coupled to ground.
  32. Lien Chuen-Der ; Shy Paul Y. M., Multiple node ESD devices.
  33. Mudd Mark S. J. (Swindon GB3) Addinall Ross (Gloucestershire GBX), Overvoltage protection circuit.
  34. Nadd Bruno C. (Puyvert FRX), Power MOSFET with overcurrent and over-temperature protection.
  35. Statz Timothy V. ; Suh Dongwook Drew ; Spielberger Kevin, Power supply ESD protection circuit.
  36. Takao Noriyuki,JPX, Protecting circuit for a semiconductor circuit.
  37. Yu Ta-Lee,TWX, Protection circuit for a CMOS integrated circuit.
  38. Ravanelli Enrico M. A.,ITX ; Fontanella Luca,ITX, Protection circuit for an electric supply line in a semiconductor integrated device.
  39. Sakurai Atsushi,JPX, Protective circuit and electric circuit using the protective circuit.
  40. Duvvury Charvaka ; Marum Steven E. ; Chatterjee Amitava, Semiconductor ESD protection circuit.
  41. Yamaguchi Yasuo,JPX, Semiconductor device.
  42. Van Roozendaal Leonardus J. (Eindhoven NLX) De Werdt Reinier (Eindhoven NLX), Semiconductor device provided with a protection circuit.
  43. Singh Ranbir ; Thoma Morgan Jones, Semiconductor device with increased parasitic emitter resistance and improved latch-up immunity.
  44. Otsuka Nobuaki,JPX, Semiconductor integrated circuit.
  45. Sasaki Nobuo (Kawasaki JPX), Semiconductor integrated circuit device providing a protection circuit.
  46. Fujii Takeo,JPX ; Narita Kaoru,JPX ; Horiguchi Yoko,JPX, Semiconductor integrated circuit with protection circuit against electrostatic discharge.
  47. Diaz Carlos H. (Urbana IL) Duvvury Charvaka (Plano TX) Kang Sung-Mo (Champaign IL), Source contact placement for efficient ESD/EOS protection in grounded substrate MOS integrated circuit.

이 특허를 인용한 특허 (38)

  1. Rahim, Irfan; Huang, Cheng Hsiung; Liu, Yow-Juang Bill; Watt, Jeffrey T.; O, Hugh Sung-Ki, Apparatus and methods for electrostatic discharge circuitry with snap-back device.
  2. Worley, Eugene R., Ballasting MOSFETs using staggered and segmented diffusion regions.
  3. Beasom, James D., Bipolar transistor for an integrated circuit having variable value emitter ballast resistors.
  4. Beasom,James D., Bipolar transistor for an integrated circuit having variable value emitter ballast resistors.
  5. Beasom, James D., Bipolar transistor having variable value emitter ballast resistors.
  6. Boyd, Graeme B.; Lye, William M.; Cheng, Xun, Compact CMOS ESD layout techniques with either fully segmented salicide ballasting (FSSB) in the source and/or drain regions.
  7. Vashchenko, Vladislav; Hopper, Peter J., Current balancing in NPN BJT and BSCR snapback devices.
  8. Abou-Khalil, Michel J.; Gauthier, Robert; Li, Hongmei; Li, Junjun; Mitra, Souvick; Putnam, Christopher S., Design structure for uniform triggering of multifinger semiconductor devices with tunable trigger voltage.
  9. May,James T.; Tyler,Larry E., Destructive electrical transient protection.
  10. Salcedo, Javier A.; Liou, Juin J.; Bernier, Joseph C.; Whitney, Donald K., Devices with adjustable dual-polarity trigger- and holding-votage/current for high level of electrostatic discharge protection in sub-micron mixed signal CMOS/BiCMOS integrated.
  11. Salcedo, Javier A.; Liou, Juin J.; Bernier, Joseph C.; Whitney, Donald K., Devices with adjustable dual-polarity trigger-and holding-voltage/current for high level of electrostatic discharge protection in sub-micron mixed signal CMOS/BiCMOS integrated.
  12. Salcedo, Javier A.; Liou, Juin J.; Bernier, Joseph C.; Whitney, Donald K., Devices with adjustable dual-polarity trigger-and holding-voltage/current for high level of electrostatic discharge protection in sub-micron mixed signal CMOS/BiCMOS integrated circuits.
  13. Ker, Ming-Dou; Lin, Chun-Yu; Wang, Chang-Tzu, ESD protection circuitry with multi-finger SCRS.
  14. Ker, Ming-Dou; Peng, Jeng-Jie; Jiang, Hsin-Chin, ESD protection design with turn-on restraining method and structures.
  15. Russ, Cornelius Christian; Alvarez, David; Chatty, Kiran V.; Schneider, Jens; Gauthier, Robert; Wendel, Martin, ESD protection device and method.
  16. Sawahata, Kouichi, ESD protection element.
  17. Lee, Chien-Hsin; Lu, Xiangxiang; Natarajan, Mahadeva Iyer, Electrostatic discharge (ESD) protection transistor devices and integrated circuits with electrostatic discharge protection transistor devices.
  18. Juang,Yih Cherng, Electrostatic discharge protection circuit.
  19. Ker, Ming-Dou; Chen, Jia-Huei; Jiang, Ryan Hsin-Chin, Electrostatic discharge protection device and layout thereof.
  20. Lai, Chun-Hsiang; Liu, Meng-Huang; Su, Shin; Lu, Tao-Cheng, Gate-equivalent-potential circuit and method for I/O ESD protection.
  21. Hébert, François; Bhalla, Anup, High power and high temperature semiconductor power devices protected by non-uniform ballasted sources.
  22. Chuang, Chien-Hui, Input/output buffer and electrostatic discharge protection circuit.
  23. Chang, Shunhua; Di Sarro, James Paul; Gauthier, Jr., Robert J.; Jack, Nathan; Mitra, Souvick, Integrated circuit protection during high-current ESD testing.
  24. Lin, Xin; Blomberg, Daniel J.; Zuo, Jiang-Kai, Method for forming a Schottky diode.
  25. Boyd, Graeme B.; Lye, William M.; Cheng, Xun, Methods for forming fully segmented salicide ballasting (FSSB) in the source and/or drain region.
  26. Kodama,Noriyuki; Sawahata,Koichi, Multifinger-type electrostatic discharge protection element.
  27. Lui, Sik K.; Bhalla, Anup, Robust semiconductor power devices with design to protect transistor cells with slower switching speed.
  28. Noguchi, Ko, Semiconductor device.
  29. Wang, Dening, Semiconductor device having a gate electrode material feature located adjacent a gate width side of its gate electrode and a method of manufacture therefor.
  30. Onda, Takamitsu, Semiconductor device having output buffers and voltage path coupled to output buffers.
  31. Kubo,Takashi, Semiconductor device with bus terminating function.
  32. Kubo,Takashi, Semiconductor device with bus terminating function.
  33. Chen, Ker Min, Serpentine ballasting resistors for multi-finger ESD protection device.
  34. Abou-Khalil, Michel J.; Gauthier, Jr., Robert; Li, Hongmei; Li, Junjun; Mitra, Souvick; Putnam, Christopher S., Structure and circuit technique for uniform triggering of multifinger semiconductor devices with tunable trigger voltage.
  35. Huang, Shao-Chang; Lee, Jian-Hsing, Tie-off circuit with ESD protection features.
  36. Ker,Ming Dou; Chuang,Che Hao, Turn-on-efficient bipolar structures for on-chip ESD protection.
  37. Ker,Ming Dou; Chuang,Che Hao; Lo,Wen Yu, Uniform turn-on design on multiple-finger MOSFET for ESD protection application.
  38. Wu, Yi-Hsu; Lee, Jian-Hsing; Chen, Shui-Hung, Whole chip ESD protection.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로