초록 ▼

The invention is embodied in a plasma reactor for processing a semiconductor wafer, the reactor having a gas distribution plate including a front plate in the chamber and a back plate on an external side of the front plate, the gas distribution plate comprising a gas manifold adjacent the back plate

The invention is embodied in a plasma reactor for processing a semiconductor wafer, the reactor having a gas distribution plate including a front plate in the chamber and a back plate on an external side of the front plate, the gas distribution plate comprising a gas manifold adjacent the back plate, the back and front plates bonded together and forming an assembly. The assembly includes an array of holes through the front plate and communicating with the chamber, at least one gas flow-controlling orifice through the back plate and communicating between the manifold and at least one of the holes, the orifice having a diameter that determines gas flow rate to the at least one hole. In addition, an array of pucks is at least generally congruent with the array of holes and disposed within respective ones of the holes to define annular gas passages for gas flow through the front plate into the chamber, each of the annular gas passages being non-aligned with the orifice.

대표청구항 ▼

The invention is embodied in a plasma reactor for processing a semiconductor wafer, the reactor having a gas distribution plate including a front plate in the chamber and a back plate on an external side of the front plate, the gas distribution plate comprising a gas manifold adjacent the back plate

The invention is embodied in a plasma reactor for processing a semiconductor wafer, the reactor having a gas distribution plate including a front plate in the chamber and a back plate on an external side of the front plate, the gas distribution plate comprising a gas manifold adjacent the back plate, the back and front plates bonded together and forming an assembly. The assembly includes an array of holes through the front plate and communicating with the chamber, at least one gas flow-controlling orifice through the back plate and communicating between the manifold and at least one of the holes, the orifice having a diameter that determines gas flow rate to the at least one hole. In addition, an array of pucks is at least generally congruent with the array of holes and disposed within respective ones of the holes to define annular gas passages for gas flow through the front plate into the chamber, each of the annular gas passages being non-aligned with the orifice. -reflective coating which has been treated with a gaseous plasma, wherein the anti-reflective coating is selected from the group consisting of silicon-rich oxides defined by the formulas SixOyand SixOy:Hn,and silicon-rich oxynitrides, defined by the formulas SixOyNzand SixOyNz:Hn,and silicon nitrides defined by the formulas SixNzand SixNz:Hn,wherein in all formulas, x, y, z, and n represent the atomic percentage of silicon, oxygen, nitrogen, and hydrogen, respectively; wherein the anti-reflective coating is deposited to a thickness range of from about 100 .ANG. to about 1000 .ANG.; wherein said photoresist layer is placed over and in direct contact with said anti-reflective coating; and wherein said gaseous plasma is N2O/He. 3. A patterned silicon structure comprising a silicon substrate; an anti-reflective coating on an upper surface of said silicon substrate, said anti-reflective coating having been treated with a gas plasma, wherein said gas plasma is N2O or N2O/He; a patterned photoresist layer placed over and in direct contact with said plasma-treated anti-reflective coating having at least one opening therein, the interface between said photoresist layer and said anti-reflective layer having no footings from said photoresist layer. 4. A patterned silicon structure as claimed in claim 3 further including an opening in said plasma-treated anti-reflective coating which lies beneath and in direct contact with said at least one opening in said pattern in said photoresist layer, said at least one opening in said pattern in said plasma-treated anti-reflective coating having substantially the same width as said opening in said photoresist layer. 5. A patterned silicon structure as claimed in claim 3 wherein said anti-reflective coating is selected from the group consisting of silicon-rich oxides defined by the formulas SixOyand SixOy:Hn,and silicon-rich oxynitrides, defined by the formulas SixOyNzand SixOyNz:Hn,and silicon nitrides defined by the formulas SixNzand SixNz:Hn,wherein in all formulas, x, y, z, and n represent the atomic percentage of silicon, oxygen, nitrogen, and hydrogen, respectively. 6. A patterned silicon structure as claimed in claim 5 wherein the anti-reflective coating is selected from the group consisting of silicon-rich oxynitrides defined by the formula SixOyNzwherein x is from about 0.36 to about 0.65, y is from about 0.02 to about 0.56, and z is from about 0.07 to about 0.33. 7. A patterned silicon structure as claimed in claim 5 wherein the anti-reflective coating is deposited on said substrate to a thickness range of from about 100 .ANG. to about 1000 .ANG.. 8. A semiconductor device comprising: at least one layer of an anti-reflective coating which has been treated with a gaseous plasma, wherein said gaseous plasma is N2O or N2O/He; and a photoresist placed over and in direct contact with said anti-reflective coating. e die pad and the lead fingers. conductor substrate is not less than 1×1018cm-3. 6. The nitride semiconductor light emitting device according to claim 1, wherein said nitride semiconductor substrate includes a layer region having a lowest impurity concentration of not more than 8×1018cm-3. 7. The nitride semiconductor light emitting device according to claim 1, wherein said first layer region of said nitride semiconductor substrate has a thickness that is not greater than 10 μm. 8. A nitride semiconductor light emitting device, comprising: a nitride semiconductor substrate; and a plurality of epitaxial growth layers including a light emitting layered structure stacked on said nitride semiconductor substrate, wherein said nitride semiconductor substrate includes at least two layer regions including a first layer region of a high impurity concentration and a second layer region of an impurity concentration that is lower than said first layer region, and the bottom of said epitaxial growth layers including a light emitting layered structure is in direct contact with said first layer region of said substrate. 9. The nitride semiconductor light emitting device according to claim 8, wherein all the layer regions in said nitride semiconductor substrate are of n-type conductivity. 10. The nitride semiconductor light emitting device according to claim 9, wherein said first layer region of said nitride semiconductor substrate includes conductivity-type determining impurities for n-type. 11. The nitride semiconductor light emitting device according to claim 8, wherein a kind of impurity included in said nitride semiconductor substrate is selected from the group consisting of silicon, germanium, oxygen, carbon, sulfur, selenium, and tellurium. 12. The nitride semiconductor light emitting device according to claim 8, wherein the impurity concentration of said first layer region of said nitride semiconductor substrate is not less than 1×1018cm-3. 13. The nitride semiconductor light emitting device according to claim 8, wherein said nitride semiconductor substrate includes a layer region having a lowest impurity concentration of not more than 8×1018cm-3. 14. The nitride semiconductor light emitting device according to claim 8, wherein said first layer region of said nitride semiconductor substrate has a thickness that is not greater than 10 μm.