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| 국가/구분 | United States(US) Patent 등록 |
|---|---|
| 국제특허분류(IPC7판) |
|
| 출원번호 | US-0964171 (2001-09-25) |
| 발명자 / 주소 |
|
| 출원인 / 주소 |
|
| 대리인 / 주소 |
|
| 인용정보 | 피인용 횟수 : 662 인용 특허 : 28 |
An input device for robotic surgery mechanically transmits a grip signal across a first joint coupling a handle to a linkage supporting the handle. The handle is removable and replaceable, allows unlimited rotation about the joint, and may optionally include a touch sensor to inhibit movement of a s
An input device for robotic surgery mechanically transmits a grip signal across a first joint coupling a handle to a linkage supporting the handle. The handle is removable and replaceable, allows unlimited rotation about the joint, and may optionally include a touch sensor to inhibit movement of a surgical end effector when the hand of the surgeon is not in contact with the handle.
An input device for robotic surgery mechanically transmits a grip signal across a first joint coupling a handle to a linkage supporting the handle. The handle is removable and replaceable, allows unlimited rotation about the joint, and may optionally include a touch sensor to inhibit movement of a s
An input device for robotic surgery mechanically transmits a grip signal across a first joint coupling a handle to a linkage supporting the handle. The handle is removable and replaceable, allows unlimited rotation about the joint, and may optionally include a touch sensor to inhibit movement of a surgical end effector when the hand of the surgeon is not in contact with the handle. s] Schouhamer Immink, The Digital Versatile Disc (DVD): System Requirements and Channel Coding; SMPTE Journal, vol. 105, No. 8, pp. 483-489, Aug. 1, 1996. Nakamura et al. "Fine Focus 1-Beam Optical Pickup System" National Technical Report, vol. 32, No. 4, pp. 72-80 (with English translation of pp. 76-77), Aug. 1986. Ogami et al. Optical Disk Technology, publ. by Radio Technology Corp., pp. 86-97 (with English translation of pp. 86-87), Feb. 1989. paratus according to claim 6, wherein when the output frequency is changed, the center frequency is changed so that a difference between the center frequency and the output frequency is lessened. 14. A signal processing circuit comprising: a data slice circuit which binarizes data read from a disk and generates binarized data; a controller for generating a control instruction as a digital signal; a PLL circuit receiving the binarized data and having a voltage controlled oscillator which controls an output frequency in accordance with a first control voltage associated with the binarized data, and which is capable of controlling a center frequency in accordance with a second control voltage as an analog signal; a converter for converting the control instruction into the second control voltage; and wherein the output frequency is changed by the first control voltage and the center frequency is changed by the second control voltage. 15. A signal processing circuit according to claim 14, further comprising a converter for converting the control instruction into the second control voltage. 16. A signal processing circuit according to claim 15, wherein the converter is connected between the PLL circuit and an interface circuit, and the controller connected to the interface circuit. 17. A signal processing circuit according to claim 14, further comprising a disk motor control circuit which rotates the disk and changing a rotation speed of the disk. 18. A signal processing circuit according to claim 14, further comprising memory means for storing the binarized data, and error correction means, operated on the basis of the output frequency, for performing error correction processing of the binarized data, and generating a correction flag and a corresponding flag. 19. A signal processing circuit according to claim 14, wherein the PLL circuit includes a first control voltage generator for generating the first control voltage, and the first control voltage generator includes a phase comparator which compares phases of the binarized data and the output frequency, and a frequency detector which detects data associated with a predetermined frequency from the binarized data. 20. A signal processing circuit according to claim 14, wherein the center frequency changes coincidently with the output frequency. 21. A signal processing circuit according to claim 14, wherein when the output frequency is changed, the center frequency is changed to be closer to the output frequency. 22. A signal processing circuit according to claim 14, wherein when the output frequency is changed, the center frequency is changed so that a difference between the center frequency and the output frequency is lessened. 23. A read apparatus comprising: a disk motor control circuit which rotates a disk; a pickup circuit which reads data from the disk; a data slice circuit which binarizes the read data and generates binarized data; a controller for generating a control instruction as a digital signal; a PLL circuit receiving the binarized data and having a voltage controlled oscillator which controls a output frequency in accordance with a first control voltage associated with the binarized data, and which is capable of controlling a center frequency in accordance with a second control voltage as an analog signal; a converter for converting the control instruction into the second control voltage; and wherein the output frequency is changed by the first control voltage and the center frequency is changed by the second control voltage. 24. A read apparatus according to claim 23, further comprising a converter for converting the control instruction into the second control voltage. 25. A read apparatus according to claim 24, wherein the converter is connected between the PLL circuit and an interface circuit, and the controller is connected to the interface circuit. 26. A read apparatus according to claim 23, further comprising memory means for storing the bina
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