$\require{mediawiki-texvc}$
  • 검색어에 아래의 연산자를 사용하시면 더 정확한 검색결과를 얻을 수 있습니다.
  • 검색연산자
검색연산자 기능 검색시 예
() 우선순위가 가장 높은 연산자 예1) (나노 (기계 | machine))
공백 두 개의 검색어(식)을 모두 포함하고 있는 문서 검색 예1) (나노 기계)
예2) 나노 장영실
| 두 개의 검색어(식) 중 하나 이상 포함하고 있는 문서 검색 예1) (줄기세포 | 면역)
예2) 줄기세포 | 장영실
! NOT 이후에 있는 검색어가 포함된 문서는 제외 예1) (황금 !백금)
예2) !image
* 검색어의 *란에 0개 이상의 임의의 문자가 포함된 문서 검색 예) semi*
"" 따옴표 내의 구문과 완전히 일치하는 문서만 검색 예) "Transform and Quantization"

특허 상세정보

Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources

국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) G06F-007/38    H03K-019/173   
미국특허분류(USC) 326/038; 326/041
출원번호 US-0841209 (2001-04-23)
발명자 / 주소
출원인 / 주소
대리인 / 주소
    MacPherson Kwok Chen & Heid LLP
인용정보 피인용 횟수 : 51  인용 특허 : 6
초록

A Variable Grain Architecture (VGA) is used for synthesizing from primitive building elements (CBE's) an appropriate amount of dynamic multiplexing capability for each given task. Unused ones of such Configurable Building Elements (CBE's) are reconfigured to carry out further logic functions in place of the dynamic multiplexing functions. Each CBE may be programmably configured to provide no more than a 2-to-1 dynamic multiplexer (2:1 DyMUX). The dynamically-selectable output of such a synthesized 2:1 DyMUX may then be output onto a shared interconnect l...

대표
청구항

A Variable Grain Architecture (VGA) is used for synthesizing from primitive building elements (CBE's) an appropriate amount of dynamic multiplexing capability for each given task. Unused ones of such Configurable Building Elements (CBE's) are reconfigured to carry out further logic functions in place of the dynamic multiplexing functions. Each CBE may be programmably configured to provide no more than a 2-to-1 dynamic multiplexer (2:1 DyMUX). The dynamically-selectable output of such a synthesized 2:1 DyMUX may then be output onto a shared interconnect l...

이 특허를 인용한 특허 피인용횟수: 51

  1. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2013028380884.
  2. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2015049015352.
  3. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2014048706916.
  4. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2009107606943.
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J.. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2015109164952.
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J.. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2013098543795.
  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2013098533431.
  8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James. Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2013098543794.
  9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James. Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements. USP2013018356161.
  10. Master, Paul L.; Uvacek, Bohumir. Apparatus and method for adaptive multimedia reception and transmission in communication environments. USP2015049002998.
  11. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements. USP2016059330058.
  12. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements. USP2014118880849.
  13. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements. USP2012088250339.
  14. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements. USP2017039594723.
  15. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements. USP2012078225073.
  16. Barus, Daniel J. Autonomous, scalable, digital system for emulation of wired-or hardware connection. USP2014088812287.
  17. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James. Communications module, device, and method for implementing a system acquisition function. USP2009117620097.
  18. Master, Paul L.; Watson, John. Configurable hardware based digital imaging apparatus. USP2009107609297.
  19. Scheuermann, W. James; Hogenauer, Eugene B.. Control node for multi-core system. USP20190110185502.
  20. Hwang,Yean Yow; van Antwerpen,Babette; Yuan,Richard. Estimating quality during early synthesis. USP2007017171633.
  21. Furtek, Frederick Curtis; Master, Paul L.. External memory controller. USP2012098266388.
  22. Furtek, Frederick Curtis; Master, Paul L.. External memory controller node. USP2014078769214.
  23. Furtek, Fredrick Curtis; Master, Paul L.. External memory controller node. USP2011077984247.
  24. Furtek, Fredrick Curtis; Master, Paul L.. External memory controller node. USP2011077979646.
  25. Beausoleil, William F.; Elmufdi, Beshara G.. Hardware emulator having a variable input primitive. USP2012018090568.
  26. Scheuermann,Walter James. Hardware implementation of the secure hash standard. USP2009027489779.
  27. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2017059665397.
  28. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2012068200799.
  29. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2010017653710.
  30. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2014078782196.
  31. Hutton, Michael D.; Lewis, David. Integrated circuits with shared interconnect buses. USP2013088519740.
  32. Sambhwani, Sharad; Heidari, Ghobad. Low I/O bandwidth method and system for implementing detection and identification of scrambling codes. USP2013058442096.
  33. Sambhwani, Sharad; Heidari, Ghobad. Low I/O bandwidth method and system for implementing detection and identification of scrambling codes. USP2010027668229.
  34. Sambhwani,Sharad; Heidari,Ghobad. Low I/O bandwidth method and system for implementing detection and identification of scrambling codes. USP2009037512173.
  35. Master, Paul L.. Method and system for achieving individualized protected space in an operating system. USP2010027660984.
  36. Master, Paul L.. Method and system for creating and programming an adaptive computing engine. USP2011017865847.
  37. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2015059037834.
  38. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2016079396161.
  39. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2013118589660.
  40. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2010077752419.
  41. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2014078767804.
  42. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2012088249135.
  43. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2010107809050.
  44. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2010107822109.
  45. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn. Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information. USP2009017478031.
  46. Master, Paul L.. Profiling of software and circuit designs utilizing data operation analyses. USP2012098276135.
  47. Master,Paul L.; Watson,John. Storage and delivery of device features. USP2009027493375.
  48. Master, Paul L.; Watson, John. System for adapting device standards after manufacture. USP2009107602740.
  49. Master, Paul L.; Watson, John. System for authorizing functionality in adaptable hardware devices. USP201109E042743.
  50. Katragadda, Ramana; Spoltore, Paul; Howard, Ric. Task definition for specifying resource requirements. USP2012018108656.
  51. Ratchev,Boris; Hwang,Yean Yow; Pedersen,Bruce. Technology mapping technique for fracturable logic elements. USP2006087100141.