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Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-007/38
  • H03K-019/173
출원번호 US-0841209 (2001-04-23)
발명자 / 주소
  • Agrawal, Om P.
  • Sharpe-Geisler, Bradley A.
  • Chang, Herman M.
  • Nguyen, Bai
  • Tran, Giap H.
출원인 / 주소
  • Lattice Semiconductor Corporation
대리인 / 주소
    MacPherson Kwok Chen & Heid LLP
인용정보 피인용 횟수 : 51  인용 특허 : 6

초록

A Variable Grain Architecture (VGA) is used for synthesizing from primitive building elements (CBE's) an appropriate amount of dynamic multiplexing capability for each given task. Unused ones of such Configurable Building Elements (CBE's) are reconfigured to carry out further logic functions in plac

대표청구항

A Variable Grain Architecture (VGA) is used for synthesizing from primitive building elements (CBE's) an appropriate amount of dynamic multiplexing capability for each given task. Unused ones of such Configurable Building Elements (CBE's) are reconfigured to carry out further logic functions in plac

이 특허에 인용된 특허 (6)

  1. Tavana Danesh (Mountain View CA) Yee Wilson K. (Tracy CA) Holen Victor A. (Saratoga CA), FPGA architecture with repeatable tiles including routing matrices and logic matrices.
  2. Ho Walford W. (Saratoga CA) Chen Chao-Chiang (Cupertino CA) Yang Yuk Y. (Foster City CA), Hierarchically-structured programmable logic array and system for interconnecting logic elements in the logic array.
  3. Leong William W. (San Francisco CA) Cliff Richard G. (Milpitas CA) McClintock Cameron (Mountain View CA), Programmable logic array device with grouped logic regions and three types of conductors.
  4. Leong William W. (San Francisco CA) Cliff Richard G. (Milpitas CA) McClintock Cameron (Mountain View CA), Programmable logic array device with grouped logic regions and three types of conductors.
  5. Cliff Richard G. (Milpitas CA) Ahanin Bahram (Cupertino CA), Programmable logic array integrated circuits with cascade connections between logic modules.
  6. Pedersen Bruce B., Programmable logic integrated circuits with partitioned logic element using shared lab-wide signals.

이 특허를 인용한 특허 (51)

  1. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  2. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  3. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  4. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
  10. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.
  11. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  12. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  13. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  14. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.
  15. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  16. Barus, Daniel J, Autonomous, scalable, digital system for emulation of wired-or hardware connection.
  17. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.
  18. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.
  19. Scheuermann, W. James; Hogenauer, Eugene B., Control node for multi-core system.
  20. Hwang,Yean Yow; van Antwerpen,Babette; Yuan,Richard, Estimating quality during early synthesis.
  21. Furtek, Frederick Curtis; Master, Paul L., External memory controller.
  22. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
  23. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  24. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  25. Beausoleil, William F.; Elmufdi, Beshara G., Hardware emulator having a variable input primitive.
  26. Scheuermann,Walter James, Hardware implementation of the secure hash standard.
  27. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  28. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  29. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  30. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  31. Hutton, Michael D.; Lewis, David, Integrated circuits with shared interconnect buses.
  32. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  33. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  34. Sambhwani,Sharad; Heidari,Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  35. Master, Paul L., Method and system for achieving individualized protected space in an operating system.
  36. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
  37. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  38. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  39. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  40. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  41. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  42. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  43. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  44. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  45. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn, Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information.
  46. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.
  47. Master,Paul L.; Watson,John, Storage and delivery of device features.
  48. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.
  49. Master, Paul L.; Watson, John, System for authorizing functionality in adaptable hardware devices.
  50. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
  51. Ratchev,Boris; Hwang,Yean Yow; Pedersen,Bruce, Technology mapping technique for fracturable logic elements.
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