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A system and method for coordinating the operation of multiple manned, remotely operated or autonomous marine vessels engaged in marine seismic data acquisition to direct cooperating vessels from one point to the next while minimizing deviations in the desired spatial configuration of assets, risk t

A system and method for coordinating the operation of multiple manned, remotely operated or autonomous marine vessels engaged in marine seismic data acquisition to direct cooperating vessels from one point to the next while minimizing deviations in the desired spatial configuration of assets, risk to vessels and seismic assets, and personnel and to obtain optimal midpoint coverage by evaluating inputs from subsystems providing positioning information for cooperating vessels, prospect coverage, vessel capabilities, environmental information, and navigation hazards.

대표청구항 ▼

A system and method for coordinating the operation of multiple manned, remotely operated or autonomous marine vessels engaged in marine seismic data acquisition to direct cooperating vessels from one point to the next while minimizing deviations in the desired spatial configuration of assets, risk t

A system and method for coordinating the operation of multiple manned, remotely operated or autonomous marine vessels engaged in marine seismic data acquisition to direct cooperating vessels from one point to the next while minimizing deviations in the desired spatial configuration of assets, risk to vessels and seismic assets, and personnel and to obtain optimal midpoint coverage by evaluating inputs from subsystems providing positioning information for cooperating vessels, prospect coverage, vessel capabilities, environmental information, and navigation hazards. ck pin. 10. The clock buffer of claim 9, wherein said first type memory module slot corresponds to a JEDEC 184-pin memory module standard. 11. The clock buffer of claim 9, wherein said second type memory module slot corresponds to a 168-pin memory module standard. 12. The clock buffer of claim 9, wherein said clock buffer further includes: an inverse tri-state buffer having an input terminal connected to said clock signal terminal and an output terminal connected to said doubly defined clock pin; and a tri-state buffer having an input terminal connected to said clock signal and an output terminal connected to said doubly defined clock pin, wherein said inverse tri-state buffer is activated and said output terminal of said tri-state buffer is in a high impedance state when said doubly defined clock pin outputs a first type memory clock signal, wherein said tri-state buffer is activated and said inverse tri-state buffer is in a high impedance state when said double defined clock pin outputs a second type memory clock signal. 13. The clock buffer of claim 9, wherein said circuit system further includes a clock generator for producing a clock signal. 14. The clock buffer of claim 9, wherein said first type memory module includes a double data rate dynamic random access memory module. 15. The clock buffer of claim 9, wherein said second type memory module includes a synchronous dynamic random access memory module. 16. The clock buffer of claim 9, wherein said circuit system further includes a control chipset coupled to said clock buffer for controlling said clock buffer such that either a first type memory clock signal or a second type memory clock signal is output. 17. The clock circuit of claim 9, wherein the first type clock signal and the second type clock signal comprises an ordinary clock signal and a differential clock signal. 18. A clock buffer for a circuit system, wherein said circuit system includes a first type memory module slot having a first type memory clock pin for receiving a first type memory clock signal and a second type memory module slot having a second type memory clock pin for receiving a second type memory clock signal, comprising: a doubly defined clock pin for outputting either said first type memory clock signal or said second type memory clock signal, wherein said clock buffer receives a clock signal and outputs said first type memory clock signal to said first type memory clock pin or outputs said second type memory clock signal to said second type memory clock pin, wherein said clock buffer further includes: an inverse tri-state buffer having an input terminal connected to said clock signal terminal and an output terminal connected to said doubly defined clock pin; and a tri-state buffer having an input terminal connected to said clock signal and an output terminal connected to said doubly defined clock pin, wherein said inverse tri-state buffer is activated and said output terminal of said tri-state buffer is in a high impedance state when said doubly defined clock pin outputs a first type memory clock signal, wherein said tri-state buffer is activated and said inverse tri-state buffer is in a high impedance state when said double defined clock pin outputs a second type memory clock signal. 19. The clock circuit of claim 18, wherein the first type clock signal and the second type clock signal comprises an ordinary dock signal and a differential clock signal. 20. A clock circuit for supporting a plurality of memory module types, wherein said clock circuit connects with a first type memory module slot and a second type memory module slot, wherein said first memory module slot has a first type memory clock pin for receiving a first type memory clock signal, wherein said second memory module slot has a second type memory clock pin for receiving a second type memory clock signal, comprising: a clock generator for producing a clock signal; and a clock buffer coupled to said first typ e memory module slot, said second memory module slot and said clock generator, wherein said clock buffer has a doubly defined clock pin for outputting either said first type memory clock signal or said second type memory clock signal, and said clock buffer also receives said clock signal and outputs a first type memory clock signal to said first type memory clock pin or outputs a second type memory clock signal to said second type memory clock pin, wherein said clock buffer further includes: an inverse tri-state buffer having an input terminal connected to said clock signal terminal and an output terminal connected to said doubly defined clock pin; and a tri-state buffer having an input terminal connected to said clock signal and an output terminal connected to said doubly defined clock pin, wherein said inverse tri-state buffer is activated and said output terminal of said tri-state buffer is in a high impedance state when said doubly defined clock pin outputs a first type memory clock signal, wherein said tri-state buffer is activated and said inverse tri-state buffer is in a high impedance state when said double defined clock pin outputs a second type memory clock signal. 21. The clock circuit of claim 20, wherein the first type clock signal and the second type clock signal comprises an ordinary clock signal and a differential clock signal.