이 특허에 인용된 특허 (89) 인용/피인용 타임라인 분석

1. Small Gary L. (Los Gatos CA), Adaptable wafer probe assembly for testing ICs with different power/ground bond pad configurations.

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2. Kardos Gabor (Sunnyvale CA), Adapter which emulates ball grid array packages.

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3. Pedder David J. (Long Compton GBX), Apparatus and method for testing bare dies with low contact resistance between the die and testing station.

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4. Isaacs Phillip Duane ; Sluzewski David Allen ; Hoffmeyer Mark Kenneth, Apparatus and method to test for known good die.

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5. Pavoni Giovanni,ITX ; Bagioni Graziano,ITX ; Antonello Gianpaolo,ITX, Automatic adjustment method for elimination of the centering error during the electrical test on printed circuit boards.

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6. Pedder David John,GBX, Bare die testing.

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7. Hubacher Eric M. (Austin TX), Bumped semiconductor device and method for probing the same.

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8. Wood Alan G. (Boise ID) Farnworth Warren M. (Nampa ID) Hembree David R. (Boise ID), Carrier for testing an unpackaged semiconductor die.

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9. Bertolet Allan ; Fiore James ; Gramatzki Eberhard, Chip design process for wire bond and flip-chip package.

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10. Chang Sung Chul ; Khandros Igor Y. ; Smith William D., Chip-scale carrier for semiconductor devices including mounted spring contacts.

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11. Manning Troy A., Circuit and method for configuring a redundant bond pad for probing a semiconductor.

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12. Ohkubo Masao (Tokyo JPX) Yoshimitsu Yasuro (Tokyo JPX), Complex probe card for testing a semiconductor wafer.

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13. Okubo Masao (Tokyo JPX) Yoshimitsu Yasuro (Tokyo JPX), Complex probe card for testing a semiconductor wafer.

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14. Benjamin N. Eldridge ; Igor Y. Khandros ; David V. Pedersen ; Ralph G. Whitten, Concurrent design and subsequent partitioning of product and test die.

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15. Farnworth Warren M. ; Wark James M. ; Nelson Eric S. ; Duesman Kevin G., Device and method for testing integrated circuit dice in an integrated circuit module.

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16. Ogusu Makoto,JPX ; Saitoh Kenji,JPX, Device manufacturing method and apparatus utilizing concentric fan-shaped pattern mask.

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17. Crowley Richard N. (Aloha OR), Driven guard probe card.

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18. Kister January, Dual contact probe assembly for testing integrated circuits.

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19. Amerasekera Ekanayake Ajith ; Duvvury Charvaka, ESD protection circuit for dual 3V/5V supply devices using single thickness gate oxides.

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20. Alcoe David James ; Sathe Sanjeev Balwant, Electronic package with compressible heatsink structure.

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21. Shiao-Shien Chen TW; Tien-Hao Tang TW, Electrostatic discharge protection circuit for multi-voltage power supply circuit.

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22. Khandros Igor Y. ; Mathieu Gaetan L., Flexible contact structure with an electrically conductive shell.

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23. Whann Welton B. (San Diego CA) Elizondo Paul M. (Escondido CA), High density probe card.

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24. Ardezzone Frank J. (Santa Clara CA), High density probe-head with isolated and shielded transmission lines.

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25. Jones Mark R. ; Khoury Theodore A., High performance integrated circuit chip package.

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26. Matsuoka Noriyuki (Yokohama JPX) Uratsuji Kazumi (Tokyo JPX), IC socket.

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27. Paul Davis Bell, Integrated circuit having wirebond pads suitable for probing.

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28. Boll Gregory G. (Naples FL) Boll Harry J. (Naples FL), Integrated circuit probing apparatus including a capacitor bypass structure.

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29. Laub Michael Frederick, Integrated circuit socket for ball grid array and land grid array lead styles.

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30. Rostoker Michael D. (San Jose CA) Dangelo Carlos (San Jose CA) Koford James (San Jose CA) Fulcher Edwin (Palo Alto CA), Integrated circuit wafer comprising unsingulated dies, and decoder arrangement for individually testing the dies.

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31. Bargain Raymond (Sartrouville FRX) Riverie Jean (Limours FRX) Ollivier Jean-Francois (Versailles FRX), Intermediate connector for use between a printed circuit card and a substrate for electronic circuits.

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32. Kister January (Palo Alto CA), Large scale protrusion membrane for semiconductor devices under test with very high pin counts.

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33. Taura Toru,JPX ; Inoue Hirobumi,JPX ; Tanehashi Masao,JPX ; Matsunaga Kouji,JPX ; Yamagishi Yuuichi,JPX ; Hayakawa Satoshi,JPX ; Tsugane Hironori,JPX, Longitudinal type high frequency probe for narrow pitched electrodes.

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34. Schwindt Randy J., Low-current probe card with reduced triboelectric current generating cables.

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35. Queyssac Daniel G., Low-profile removable ball-grid-array integrated circuit package.

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36. Leedy Glenn J. (1061 E. Mountain Dr. Santa Barbara CA 93108), Making and testing an integrated circuit using high density probe points.

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37. Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Making discrete power connections to a space transformer of a probe card assembly.

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38. Crumly William R. (Anaheim CA), Membrane connector with stretch induced micro scrub.

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39. Sugai Maureen (Phoenix AZ), Method and apparatus for coupling a semiconductor device with a tester.

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40. Kalter Howard L. ; Pogge H. Bernhard ; Prokop George S. ; Wheater Donald L., Method for chip testing.

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41. Akram Salman ; Hembree David R., Method for fabricating semiconductor interconnect having test structures for evaluating electrical characteristics of the interconnect.

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42. Littlebury Hugh W. (Chandler AZ), Method for parallel testing of semiconductor devices.

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43. Ports Kenneth A. (Indialantic FL) St. Clair Thomas R. (Melbourne FL), Method for qualifying biased burn-in integrated circuits on a wafer level.

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44. Malhi Satwinder (Garland TX) Kwon Oh-Kyong (Richardson TX), Method of forming an apparatus for burn in testing of integrated circuit chip.

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45. Khandros Igor Y. (Peekskil NY), Method of manufacturing electrical contacts, using a sacrificial member.

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46. Kasai Kunihiro,JPX, Method of manufacturing semiconductor device having a test pad.

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47. Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Method of planarizing tips of probe elements of a probe card assembly.

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48. Leedy Glenn J. (Santa Barbara CA), Method of repairing an integrated circuit structure.

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49. Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Method of temporarily, then permanently, connecting to a semiconductor device.

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50. Devereaux Kevin M. (Boise ID) Bunn Mark (Boise ID) Higgins Brian (Boise ID), Method of testing individual dies on semiconductor wafers prior to singulation.

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51. Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Method of testing semiconductor.

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52. Ma Manny Kin F., Methods and structures for pad reconfiguration to allow intermediate testing during manufacture of an integrated circuit.

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53. Swapp Mavin (Mesa AZ), Micromachined semiconductor probe card.

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54. Tran Allen, Multi-layered shielded substrate antenna.

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55. Evans Arthur (Broofield Center CT), Multi-level test probe assembly for IC chips.

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56. Puar Deepraj S. (Sunnyvale CA), Multiple probing of an auxilary test pad which allows for reliable bonding to a primary bonding pad.

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57. Elder Richard A. (Dallas TX) Johnson Randy (Carrollton TX) Frew Dean L. (Garland TX) Wilson Arthur M. (Dallas TX), Non-destructive burn-in test socket for integrated circuit die.

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58. Smith Donald L. (Palo Alto CA) Alimonda Andrew S. (Los Altos CA), Photolithographically patterned spring contact.

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59. Driller Hubert (Schmitten DEX) Mang Paul (Schmitten DEX), Printed circuit board testing device with foil adapter.

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60. Higgins H. Dan ; Martinez Martin A. ; Bates R. Dennis, Probe assembly and method for switchable multi-DUT testing of integrated circuit wafers.

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61. Higgins H. Dan (323 E. Redfield Chandler AZ 85225), Probe card apparatus.

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62. Carlin Scott J. (Austin TX) Roberts ; Jr. Samuel (Austin TX), Probe card apparatus having a heating element and process for using the same.

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63. Higgins H. Dan ; Pandey Rajiv ; Armendariz Norman J. ; Bates R. Dennis, Probe card assembly for high density integrated circuits.

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64. Trenary Dale T. (San Jose CA), Probe card for integrated circuit chip.

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65. Doherty C. Patrick ; deVarona Jorge L. ; Akram Salman, Probe card having on-board multiplex circuitry for expanding tester resources.

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66. Okubo Kazumasa (Kanagawa JPX) Okubo Masao (Nishinomiya JPX) Yoshimitsu Yasuro (Takatsuki JPX) Sugaya Kiyoshi (Amagasaki JPX), Probe card in which contact pressure and relative position of each probe end are correctly maintained.

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67. Nakano Shoukichi (Kawasaki JPX), Prober for semiconductor integrated circuit element wafer.

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68. Atkins Glen G. (Boise ID) Cohen Michael S. (Boise ID) Mauritz Karl H. (Eagle ID) Shaffer James M. (Boise ID), Repairable wafer scale integration system.

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69. Ahmad Aftab (Boise ID) Weber Larren G. (Caldwell ID) Green Robert S. (Boise ID), Semiconductor array having built-in test circuit for wafer level testing.

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70. Grube Gary (Monroe NY) Khandros Igor (Peekskill NY) Mathieu Gaetan (Carmel NY), Semiconductor chip assemblies and components with pressure contact.

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71. King Jerrold L. (Boise ID) Brooks Jerry M. (Caldwell ID), Semiconductor chip package.

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72. Sahara Hiroshi (Yokohama JPX), Semiconductor device.

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73. Waki Masaki,JPX, Semiconductor device having tab-leads and a fabrication method thereof.

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74. Akito Yoshida JP, Semiconductor device with flip-chip structure and method of manufacturing the same.

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75. Higashi Tatsushi,JPX ; Kuroda Akihiro,JPX ; Tosa Hiroaki,JPX, Semiconductor device with test terminal and IC socket.

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76. Kurisu Masakazu (Tokyo JPX), Semiconductor integrated circuit device.

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77. Isaac George L. ; Miller Donald C. ; Ziegenhagen ; II Rodney Scott, Semiconductor test socket and contacts.

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78. Yamada Toshio (Osaka JPX) Fujiwara Atsushi (Kyoto JPX) Inoue Michihiro (Nara JPX) Matsuyama Kazuhiro (Osaka JPX), Semiconductor testing apparatus, semiconductor testing circuit chip, and probe card.

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79. Briggs Merton Darrell ; Miller Alfred H., Socket including centrally distributed test tips for testing unpackaged singulated die.

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80. Dozier ; II Thomas H. ; Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Sockets for electronic components and methods of connecting to electronic components.

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81. Khandros Igor Y. ; Pedersen David V., Stacking semiconductor devices, particularly memory chips.

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82. Grabbe Dimitry G. (Middletown PA) Korsunsky Iosif (Harrisburg PA), Tandem loop contact for an electrical connector.

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83. Hembree David R., Temporary semiconductor package having hard-metal, dense-array ball contacts and method of fabrication.

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84. Ikeya Kiyokazu,JPX ; Padovani Francois A., Test socket for detachable IC chip.

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85. Rostoker Michael D. (San Jose CA) Dangelo Carlos (San Jose CA) Koford James (San Jose CA), Testing and exercising individual, unsingulated dies on a wafer.

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86. Rostoker Michael D. (San Jose CA) Dangelo Carlos (San Jose CA) Koford James (San Jose CA), Testing and exercising individual, unsingulated dies on a wafer.

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87. Rostoker Michael D. ; Dangelo Carlos ; Koford James, Testing and exercising individual, unsingulated dies on a wafer.

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88. Shiraishi Shogo (Kitakyushu JPX), Universal probe card for use in a semiconductor chip die sorter test.

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89. Khandros Igor Y. ; Pedersen David V., Wafer-level burn-in and test.

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이 특허를 인용한 특허 (75) 인용/피인용 타임라인 분석

1. Siddiquie, Adnan A.; Dai, Fangyong, Active pin connection monitoring system and method.

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2. Strid, Eric; Gleason, K. Reed, Active wafer probe.

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3. Strid,Eric; Gleason,K. Reed, Active wafer probe.

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4. Perry,Guy, Bond pad structure comprising multiple bond pads with metal overlap.

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5. Strid, Eric; Campbell, Richard, Calibration structures for differential signal probing.

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6. Rutten, Ivo Wilhelmus Johannes Marie, Chip-mounted contact springs.

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7. Hill,Michael J.; Shi,Weimin, Control of breakdown voltage for microelectronic packaging.

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8. Campbell, Richard; Strid, Eric W.; Andrews, Mike, Differential signal probe with integral balun.

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9. Strid, Eric; Campbell, Richard, Differential signal probing system.

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10. Campbell, Richard L.; Andrews, Michael, Differential waveguide probe.

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11. Burcham, Terry; McCann, Peter; Jones, Rod, Double sided probing structures.

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12. Burcham,Terry; McCann,Peter; Jones,Rod, Double sided probing structures.

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13. Andrews, Peter; Hess, David; New, Robert, Interface for testing semiconductors.

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14. Tervo,Paul A.; Cowan,Clarence E., Low-current pogo probe card.

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15. Tervo,Paul A.; Cowan,Clarence E., Low-current pogo probe card.

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16. Schwindt,Randy J., Low-current probe card.

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17. Gleason, K. Reed; Bayne, Michael A.; Smith, Kenneth; Lesher, Timothy; Koxxy, Martin, Membrane probing method using improved contact.

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18. Gleason, Reed; Bayne, Michael A.; Smith, Kenneth; Lesher, Timothy; Koxxy, Martin, Membrane probing method using improved contact.

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19. Gleason, K. Reed; Smith, Kenneth R.; Bayne, Mike, Membrane probing structure with laterally scrubbing contacts.

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20. Gleason, Reed; Bayne, Michael A.; Smith, Kenneth; Lesher, Timothy; Koxxy, Martin, Membrane probing system.

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21. Gleason,Reed; Bayne,Michael A.; Smith,Kenneth; Lesher,Timothy; Koxxy,Martin, Membrane probing system.

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22. Gleason,Reed; Bayne,Michael A.; Smith,Kenneth; Lesher,Timothy; Koxxy,Martin, Membrane probing system.

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23. Smith,Kenneth; Gleason,Reed, Membrane probing system.

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24. Smith,Kenneth; Gleason,Reed, Membrane probing system.

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25. Tervo,Paul A.; Smith,Kenneth R.; Cowan,Clarence E.; Dauphinais,Mike P.; Koxxy,Martin J., Membrane probing system.

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26. Tervo,Paul A.; Smith,Kenneth R.; Cowan,Clarence E.; Dauphinais,Mike P.; Koxxy,Martin J., Membrane probing system.

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27. Gleason, K. Reed; Smith, Kenneth R.; Bayne, Mike, Membrane probing system with local contact scrub.

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28. Gleason,K. Reed; Smith,Kenneth R.; Bayne,Mike, Membrane probing system with local contact scrub.

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29. Wang, Seongmoon; Chakradhar, Srimat T., Method and apparatus for structured ASIC test point insertion.

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30. Brodsky,William Louis; Hoffmeyer,Mark Kenneth; Stack,James R., Method and structure for implementing enhanced interconnection performance of a land grid array (LGA) module and a printed wiring board.

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31. Gleason,Reed; Bayne,Michael A.; Smith,Kenneth, Method for constructing a membrane probe using a depression.

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32. Hayden, Leonard; Martin, John; Andrews, Mike, Method of assembling a wafer probe.

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33. Gleason, Reed; Bayne, Michael A.; Smith, Kenneth, Method of constructing a membrane probe.

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34. Perry,Guy, Method of forming a bond pad structure.

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35. Smith, Kenneth R., Method of replacing an existing contact of a wafer probing assembly.

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36. Strid,Eric; Campbell,Richard, On-wafer test structures for differential signals.

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37. Tervo,Paul A.; Cowan,Clarence E., POGO probe card for low current measurements.

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38. Hayden,Leonard; Rumbaugh,Scott; Andrews,Mike, Probe for combined signals.

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39. Hayden,Leonard; Rumbaugh,Scott; Andrews,Mike, Probe for combined signals.

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40. Hayden,Leonard; Rumbaugh,Scott; Andrews,Mike, Probe for combined signals.

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41. Hayden,Leonard; Rumbaugh,Scott; Andrews,Mike, Probe for combined signals.

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42. Hayden,Leonard; Rumbaugh,Scott; Andrews,Mike, Probe for combined signals.

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43. Campbell,Richard L.; Andrews,Michael; Bui,Lynh, Probe for high frequency signals.

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44. Gleason,K. Reed; Lesher,Tim; Strid,Eric W.; Andrews,Mike; Martin,John; Dunklee,John; Hayden,Leonard; Safwat,Amr M. E., Probe for testing a device under test.

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45. Smith, Kenneth; Jolley, Michael; Van Syckel, Victoria, Probe head having a membrane suspended probe.

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46. Smith,Kenneth; Jolley,Michael; Van Syckel,Victoria, Probe head having a membrane suspended probe.

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47. Schwindt,Randy, Probe holder for testing of a test device.

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48. Smith, Kenneth R.; Hayward, Roger, Probing apparatus with impedance optimized interface.

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49. Smith, Kenneth R., Replaceable coupon for a probing apparatus.

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50. Sato,Tsunehiro; Hayashi,Kiyotaka, Semiconductor device.

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51. Miyatake, Toshio; Nagata, Tatsuya; Shimizu, Hiroya; Kohno, Ryuji; Aoki, Hideyuki, Semiconductor device and test device for same.

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52. Kobayashi, Tatehito, Semiconductor device with electrode pad having probe mark.

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53. Kobayashi,Tatehito, Semiconductor device with electrode pad having probe mark.

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54. Kang, Khil-Ohk, Semiconductor memory device.

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55. Gleason,K. Reed; Lesher,Tim; Strid,Eric W.; Andrews,Mike; Martin,John; Dunklee,John; Hayden,Leonard; Safwat,Amr M. E., Shielded probe for high-frequency testing of a device under test.

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56. Gleason, K. Reed; Lesher, Tim; Strid, Eric W.; Andrews, Mike; Martin, John; Dunklee, John; Hayden, Leonard; Safwat, Amr M. E., Shielded probe for testing a device under test.

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57. Gleason,K. Reed; Lesher,Tim; Andrews,Mike; Martin,John, Shielded probe for testing a device under test.

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58. Gleason,K. Reed; Lesher,Tim; Andrews,Mike; Martin,John, Shielded probe for testing a device under test.

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59. Gleason,K. Reed; Lesher,Tim; Andrews,Mike; Martin,John, Shielded probe for testing a device under test.

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60. Gleason,K. Reed; Lesher,Tim; Andrews,Mike; Martin,John, Shielded probe for testing a device under test.

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61. Gleason,K. Reed; Lesher,Tim; Strid,Eric W.; Andrews,Mike; Martin,John; Dunklee,John; Hayden,Leonard; Safwat,Amr M. E., Shielded probe for testing a device under test.

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62. Gleason,K. Reed; Lesher,Tim; Strid,Eric W.; Andrews,Mike; Martin,John; Dunklee,John; Hayden,Leonard; Safwat,Amr M. E., Shielded probe for testing a device under test.

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63. Gleason,K. Reed; Lesher,Tim; Strid,Eric W.; Andrews,Mike; Martin,John; Dunklee,John; Hayden,Leonard; Safwat,Amr M. E., Shielded probe with low contact resistance for testing a device under test.

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64. Geerlings, Jurgen, Switched probe contact.

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65. Andrews, Peter; Hess, David, System for testing semiconductors.

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66. Eldridge, Benjamin N.; Khandros, Igor Y.; Pedersen, David V.; Whitten, Ralph G., Test assembly including a test die for testing a semiconductor product die.

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67. Eldridge, Benjamin N.; Khandros, Igor Y.; Pedersen, David V.; Whitten, Ralph G., Test assembly including a test die for testing a semiconductor product die.

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68. Viraraghavan, Janakiraman; Raghavan, Ramesh; Jayaraman, Balaji; Kempanna, Thejas; Tummuru, Rajesh R.; Kirihata, Toshiaki, Test method and structure for integrated circuits before complete metalization.

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69. Campbell, Richard, Test structure and probe for differential signals.

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70. Campbell,Richard, Test structure and probe for differential signals.

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71. Hayden, Leonard; Martin, John; Andrews, Mike, Wafer probe.

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72. Hayden,Leonard; Martin,John; Andrews,Mike, Wafer probe.

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73. Hayden,Leonard; Martin,John; Andrews,Mike, Wafer probe.

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74. Hayden,Leonard; Martin,John; Andrews,Mike, Wafer probe.

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75. Campbell, Richard, Wideband active-passive differential signal probe.

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