초록 ▼

Within a transmission channel in a frequency domain transmission medium, a plurality of non-contiguous channel portions are selected for data transmission. The selected channel portions are separated in frequency by unused channel portions. A transmitter generates a data frame of predetermined lengt

Within a transmission channel in a frequency domain transmission medium, a plurality of non-contiguous channel portions are selected for data transmission. The selected channel portions are separated in frequency by unused channel portions. A transmitter generates a data frame of predetermined length for transmission, comprising a payload and an error detection portion. The frame length is equal to the length which would map for transmission into a symbol in the transmission channel if the entire channel were selected for transmission. The payload contains a header and a data portion, into which the transmitter inserts data bytes and a number of padding bytes. Block coding error correction is performed on the padded payload to generate error detection bytes to fill the error detection portion. The frame is then mapped into the frequency domain for transmission such that the header, data and error detection bytes map into the selected channel portions and the padding bytes map into the unused channel portions and are not transmitted. At a receiver, the padding bytes are reinstated and error detection performed to correct transmission errors in the header and the data. The corrected data is then extracted from the frame.

대표청구항 ▼

Within a transmission channel in a frequency domain transmission medium, a plurality of non-contiguous channel portions are selected for data transmission. The selected channel portions are separated in frequency by unused channel portions. A transmitter generates a data frame of predetermined lengt

Within a transmission channel in a frequency domain transmission medium, a plurality of non-contiguous channel portions are selected for data transmission. The selected channel portions are separated in frequency by unused channel portions. A transmitter generates a data frame of predetermined length for transmission, comprising a payload and an error detection portion. The frame length is equal to the length which would map for transmission into a symbol in the transmission channel if the entire channel were selected for transmission. The payload contains a header and a data portion, into which the transmitter inserts data bytes and a number of padding bytes. Block coding error correction is performed on the padded payload to generate error detection bytes to fill the error detection portion. The frame is then mapped into the frequency domain for transmission such that the header, data and error detection bytes map into the selected channel portions and the padding bytes map into the unused channel portions and are not transmitted. At a receiver, the padding bytes are reinstated and error detection performed to correct transmission errors in the header and the data. The corrected data is then extracted from the frame. agement controller having an embedded JTAG test routine operable to test the at least one component IC chip; and the management controller further operable to save a JTAG test routine result for the at least one component IC chip within a test log within the memory, the test log operable to store JTAG test routine results from a plurality of JTAG tests. 10. The computer system of claim 9 further comprising the management controller operable to automatically test the at least one component IC chip during computer system boot up. 11. The computer system of claim 9 further comprising the management controller operable to selectively test the at least one component IC chip. 12. The computer system of claim 9 wherein the management controller further comprises: an embedded server boot initialization system test; and the embedded JTAG test routine associated with the embedded server boot initialization system test. 13. A method for testing on-board components in a computer system comprising: installing a JTAG test routine in a management controller associated with the computer system; testing at least one on-board component IC chip using the JTAG test routine associated with the management controller; and saving test results from the JTAG test routine in a test log operable to store JTAG test routine results from a plurality of JTAG tests. 14. The method of claim 13 further comprising testing during a boot up of the computer system. 15. The method of claim 13 wherein testing further comprises selectively testing the at least one on-board component IC chip. 16. The method of claim 13 further comprising evaluating the at least one on-board component IC chip using the test log. 17. The method of claim 13 further comprises: accessing the test log from a remote system; and evaluating the at least one on-board component IC chip using the at least two JTAG test routine results stored within the test log. 18. The method of claim 17 wherein accessing further comprises remotely accessing the test log.