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A landfill (10) having a leachate collection apparatus including a layer of geonet material (40) disposed above a liner (38) as its primary leachate flow path. Leachate flows along the geonet material to a collection trench (16) located along an edge (14) of a generally planar landfill area (12). Th

A landfill (10) having a leachate collection apparatus including a layer of geonet material (40) disposed above a liner (38) as its primary leachate flow path. Leachate flows along the geonet material to a collection trench (16) located along an edge (14) of a generally planar landfill area (12). The superior hydraulic conductivity of the geonet material (34) disposed above a liner (32) is provided below the primary drainage layer for additional ground water protection. A collection box 918) having both a leachate collection compartment (54) and a leakage collection compartment (56) is disposed in alignment with openings (80, 82) formed in the respective liner layers. The sealing surfaces (64,68) between the collection box and liners are all located on upper surfaces of the collection box.

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A landfill (10) having a leachate collection apparatus including a layer of geonet material (40) disposed above a liner (38) as its primary leachate flow path. Leachate flows along the geonet material to a collection trench (16) located along an edge (14) of a generally planar landfill area (12). Th

A landfill (10) having a leachate collection apparatus including a layer of geonet material (40) disposed above a liner (38) as its primary leachate flow path. Leachate flows along the geonet material to a collection trench (16) located along an edge (14) of a generally planar landfill area (12). The superior hydraulic conductivity of the geonet material (34) disposed above a liner (32) is provided below the primary drainage layer for additional ground water protection. A collection box 918) having both a leachate collection compartment (54) and a leakage collection compartment (56) is disposed in alignment with openings (80, 82) formed in the respective liner layers. The sealing surfaces (64,68) between the collection box and liners are all located on upper surfaces of the collection box. nd plurality of registers which are usable as logic registers and scan registers; and a test controller, coupled to the core and the peripheral logic circuit, having an input for receiving at least a control signal generated external to the integrated circuit, wherein during the test mode the programmable clock generator is further characterized as generating a base clock having a base period and a chopped clock at the fist output comprising a series of pulses of a firs t pulse width, wherein the first pulse width is less than or equal to approximately one half of the base period and wherein the pulses occur no more than once per base period; and wherein the programmable clock generator is further characterized as providing a pulse of the series of pulses selectable at any location within the base period, said location selected by a chop control signal provided external from the integrated circuit, wherein said provided pulse is provided before any other pulse that is within the base period is provided by the programmable clock generator. 2. The integrated circuit of claim 1, wherein the pulse of the series of pulses is selected to be located at one of at least four locations. 3. The integrated circuit of claim 2, wherein the programmable clock generator provides consecutive first and second pulses in consecutive first and second base periods, wherein the first pulse is at a last location of the first base period and the second pulse is at an earliest location of the second base period. 4. A method for testing an integrated circuit having a predetermined function and comprising scan test registers, comprising: providing a programmable clock pulse means on the integrated circuit for generating a clock pulse which occurs at one pulse per base period at a programmable location within the base period, wherein said generated clock pulse is generated before any other pulse that is within the base period is generated by the programmable clock pulse means: loading test data into the scan register from a source external to the integrated circuit in response to the clock; and performing a timing verification test in response to the clock pulse after the completion of loading the test data; wherein the clock pulse for all but the last load of test data occurs in response to the clock pulse being in a first location within the base period, the last load occurs in response to the clock pulse being in a second predetermined location with in the base period and is different form the first predetermined location, and the performing the timing verification occurs in response to the clock pulse being at a third predetermined location within the base period, wherein said third predetermined location is different from the second predetermined location. 5. An integrated circuit, comprising; a circuit having a predetermined function and comprising scan test registers loaded in response to a clock pulse; and a programmable clock generator means, having an input for receiving an external clock defining a base period, for providing the clock pulse to the scan test register at one pulse per base period at selectable locations in the base period wherein said provided clock pulse is provided before any other pulse that is within the base period is provided by the programmable clock pulse means. 6. The integrated circuit of claim 5, wherein the programmable clock generator means comprises: a phase locked loop having an input for receiving the external clock; and a programmable chopper, coupled to the phase locked loop, and having an output which outputs the clock pulse. 7. The integrated circuit of claim 6, wherein phase locked loop is further characterized as multiplying the external clock. 8. The integrated circuit of claim 7, wherein the programmable clock generator comprises: a plurality of registers which store chopper information; and a mulitplexer, coupled to the plurality of registers, having an output coupled to the p rogrammable chopper. 9. The integrated circuit of claim 8, wherein the multiplexer has a control input for receiving an external control signal. 10. The integrated circuit of claim 9, wherein the programmable chopper is further characterized as being a divider.