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A multilayered electronic component with or without inter-layer connections created by a process using radiation curing such as ultraviolet/electron beam curing techniques. UV light or electron beam curable binders are mixed with ceramic powders and metals powders to form a ceramic slurry and electr

A multilayered electronic component with or without inter-layer connections created by a process using radiation curing such as ultraviolet/electron beam curing techniques. UV light or electron beam curable binders are mixed with ceramic powders and metals powders to form a ceramic slurry and electrode ink, there is little or no solvent in the metal ink and ceramic slurry. Instead of drying, a UV or electron beam is used for curing the binders. These binders could contain UV/electron beam curable monomers or oligomers, photo initiators, and other additives to provide the desired chemical and physical properties in the forming process.

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A multilayered electronic component with or without inter-layer connections created by a process using radiation curing such as ultraviolet/electron beam curing techniques. UV light or electron beam curable binders are mixed with ceramic powders and metals powders to form a ceramic slurry and electr

A multilayered electronic component with or without inter-layer connections created by a process using radiation curing such as ultraviolet/electron beam curing techniques. UV light or electron beam curable binders are mixed with ceramic powders and metals powders to form a ceramic slurry and electrode ink, there is little or no solvent in the metal ink and ceramic slurry. Instead of drying, a UV or electron beam is used for curing the binders. These binders could contain UV/electron beam curable monomers or oligomers, photo initiators, and other additives to provide the desired chemical and physical properties in the forming process. ng the doped SiO2layer and the doped polysilicon layer to expose the silicon nitride layer. 10. The method of claim 1, further comprising covering the sidewalls of the trench with a thin dielectric structure prior to depositing the undoped polysilicon layer. 11. The method of claim 10, further comprising treating the thin dielectric structure with one of NO, N2O, and N ion implantation and subsequently heat treating the implanted thin dielectric structure prior to depositing the undoped polysilicon layer. 12. The method of claim 1, further comprising covering the sidewalls of the trench with a thin thermal oxynitride dielectric film prior to depositing the undoped polysilicon layer. 13. The method of claim 1, further comprising etching the trench to have a width of the trench of about 1350 .ANG., the forming of the multiple layer structure comprising: depositing from about 200 .ANG. to about 700 .ANG. of silicon to form the silicon layer; forming the pad oxide layer to be from about 50 .ANG. to about 80 .ANG.; and depositing from about 500 .ANG. to about 800 .ANG. of silicon nitride to form the silicon nitride layer. 14. The method of claim 13, wherein the depositing of the undoped polysilicon layer comprises depositing from about 100 .ANG. to about 200 .ANG. of undoped polysilicon to form the undoped polysilicon layer. 15. A method for forming an isolation trench in a semiconductor structure on a silicon-on-insulator substrate comprising; forming the semiconductor structure to be a multiple layer structure including a silicon layer, a pad oxide layer above the silicon layer, a silicon nitride layer above the pad oxide layer, and one of a doped polysilicon layer and a doped SiO2,layer above the silicon nitride layer forming a trench having a bottom and sidewalk in the semiconductor structure; depositing an undoped polysilicon layer on the bottom and the sidewalk of the trench and on a surface of a region of the semiconductor structure adjacent to the trench, the undoped polysilicon layer being deposited such that a substantial portion of the trench is left unfilled; heat treating the region adjacent to the trench to drive dopants from the one of the doped polysilicon layer and the doped SiO2layer into the undoped polysilicon layer thereby forming a secondarily doped polysilicon layer from the undoped polysilicon layer wet etching the secondarily doped polysilicon layer and the one of the doped polysilicon layer and the doped SiO2layer to remove the secondarily doped polysilicon layer and the one of the doped polysilicon layer and the doped SiO2,layer and to expose the silicon nitride layer and subsequently oxidizing the polysilicon layer to form a thermal oxide that fills the trench and thereby avoids forming a birds-beak formation of the thermal oxide above the sidewalls of the trench and avoids reduction in active device area in said adjacent semiconductor region. 16. The method of claim 15, further comprising planarizing the semiconductor structure and trench prior to oxidizing the polysilicon layer to remove the polysilicon layer from the surface of the region adjacent to the trench and to adjust the polysilicon layer in the trench such that the polysilicon layer in the trench does not extend above the surface of the silicon-on-insulator substrate adjacent to the trench. 17. The method of claim 15, further comprising removing the thermal oxide from the surface of the region adjacent to the trench using a chemo-mechanical polishing process. 18. The method of claim 17, further comprising planarizing the semiconductor structure by etching the thermal oxide and the surface of the region adjacent to the trench subsequent to the chemo-mechanical polishing process such that the thermal oxide is planar with the surface of the region adjacent to the trench. 19. The method of claim 15, the forming of the multiple layer structure comprising: depo