초록 ▼

An apparatus comprising one or more first processors and one or more second processors. The one or more first processors may each comprise a first random access memory (RAM) sections. The one or more second processors may each comprise a read only memory (ROM) section and a second RAM section. The o

An apparatus comprising one or more first processors and one or more second processors. The one or more first processors may each comprise a first random access memory (RAM) sections. The one or more second processors may each comprise a read only memory (ROM) section and a second RAM section. The one or more first processors may be configured to operate in either (i) a first mode that executes code stored in the one or more ROM sections or (ii) a second mode that processes code stored in the one or more first RAM sections. The one or more second processors may be configured to execute code from either (i) the one or more ROM sections or (ii) the one or more second RAM sections. The apparatus may provide interoperability that may increase system observability and decrease system debugging complexity.

대표청구항 ▼

An apparatus comprising one or more first processors and one or more second processors. The one or more first processors may each comprise a first random access memory (RAM) sections. The one or more second processors may each comprise a read only memory (ROM) section and a second RAM section. The o

An apparatus comprising one or more first processors and one or more second processors. The one or more first processors may each comprise a first random access memory (RAM) sections. The one or more second processors may each comprise a read only memory (ROM) section and a second RAM section. The one or more first processors may be configured to operate in either (i) a first mode that executes code stored in the one or more ROM sections or (ii) a second mode that processes code stored in the one or more first RAM sections. The one or more second processors may be configured to execute code from either (i) the one or more ROM sections or (ii) the one or more second RAM sections. The apparatus may provide interoperability that may increase system observability and decrease system debugging complexity. ter finalizing non-live objects during the garbage collecting. 8. A computer-readable medium bearing instructions for managing memory in a run-time environment, said instructions being arranged to cause one or more processors upon execution thereby to perform the steps of: accessing an object by means of an external reference, wherein said accessing includes the steps of: extracting an index from the external reference; fetching a pointer value from an entry in a value array at a position indicated by the index; if the pointer value is a null value, then performing the steps of: fetching a descriptor from an entry in a descriptor array at a position indicated by the index; initializing the object based on the descriptor; and registering a routine to deactivate the object at an end of a call; and executing the routine to deactivate the object at the end of the call. 9. The computer-readable medium according to claim 8, wherein: the executing of the routine to deactivate the object includes setting the object to null. 10. The computer-readable medium according to claim 8, further comprising the step of: garbage collecting the object at the end of the call, wherein the executing of the routine to deactivate the object is performed after finalizing non-live objects during the garbage collecting.