IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0567230
(2000-05-09)
|
우선권정보 |
KR-0016629 (1999-05-10); KR-0008698 (2000-02-23) |
발명자
/ 주소 |
|
출원인 / 주소 |
- Portable Pools Incorporated
|
대리인 / 주소 |
|
인용정보 |
피인용 횟수 :
5 인용 특허 :
5 |
초록
▼
A prefabricated swimming pool including a pool frame having a plurality of vertical frames and horizontal frames connected between the vertical frames, and a pool body fabricated from a synthetic resin sheet having a base unit and a circumferential side wall and supported by the pod frame. Storing a
A prefabricated swimming pool including a pool frame having a plurality of vertical frames and horizontal frames connected between the vertical frames, and a pool body fabricated from a synthetic resin sheet having a base unit and a circumferential side wall and supported by the pod frame. Storing and carrying of the swimming pool is simple and handy, and thane is no possibility that the circumferential side wall is inclined or collapses, ensuring a safe and stable use.
대표청구항
▼
A prefabricated swimming pool including a pool frame having a plurality of vertical frames and horizontal frames connected between the vertical frames, and a pool body fabricated from a synthetic resin sheet having a base unit and a circumferential side wall and supported by the pod frame. Storing a
A prefabricated swimming pool including a pool frame having a plurality of vertical frames and horizontal frames connected between the vertical frames, and a pool body fabricated from a synthetic resin sheet having a base unit and a circumferential side wall and supported by the pod frame. Storing and carrying of the swimming pool is simple and handy, and thane is no possibility that the circumferential side wall is inclined or collapses, ensuring a safe and stable use. Hardware Subroutine Protocol for FPGAs," Masters Thesis, MIT, Deparment of EEC, May 16, 1994, pp. 1-55; Also available as MIT/LCS Technical Report. Jones, "A Time-Multiplexed FPGA Architecture for Logic Emulation," Masters Thesis, University of Toronto, Department of EEC, 1995, pp. 1-103. Hanono, "InnerView Hardware Debugger: A Logic Analysis Tool for the Virtual Wires Emulation System," Masters Thesis, MIT, Department of EEC, Jan. 20, 1995, pp. 1-59; Also available as MIT/LCS Technical Report. Tessier, "Virtual Wires Pictures," article from webmaster@cag.lcs.mit.edu, Feb. 3, 1995, two pages. Babb, et al. "More Virtual Wires," article from webmaster@cag.lcs.mit.edu, Feb. 3, 1995, one page. Pak K. Chan, et al.; Architectural Tradeoffs in Field-Programmable-Device-Based Computing Systems, IEEE 1993; pp. 152-161.
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