IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0943899
(2001-08-30)
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발명자
/ 주소 |
- Swedlow, David
- Fein, Michael E.
- Mannheimer, Paul D.
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출원인 / 주소 |
|
대리인 / 주소 |
Townsend and Townsend and Crew LLP
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인용정보 |
피인용 횟수 :
136 인용 특허 :
37 |
초록
▼
The present invention provides a memory chip for use in an oximeter sensor, or an associated adapter or connector circuit. The memory chip allows the storing of patient related data, such as patient trending data or a patient ID, to provide enhanced capabilities for the oximeter sensor. In addition
The present invention provides a memory chip for use in an oximeter sensor, or an associated adapter or connector circuit. The memory chip allows the storing of patient related data, such as patient trending data or a patient ID, to provide enhanced capabilities for the oximeter sensor. In addition to providing unique data to store in such a memory, the present invention include unique uses of the data stored in such a memory.
대표청구항
▼
The present invention provides a memory chip for use in an oximeter sensor, or an associated adapter or connector circuit. The memory chip allows the storing of patient related data, such as patient trending data or a patient ID, to provide enhanced capabilities for the oximeter sensor. In addition
The present invention provides a memory chip for use in an oximeter sensor, or an associated adapter or connector circuit. The memory chip allows the storing of patient related data, such as patient trending data or a patient ID, to provide enhanced capabilities for the oximeter sensor. In addition to providing unique data to store in such a memory, the present invention include unique uses of the data stored in such a memory. nductor, and the transconductance is an NMOS device. 19. The transmitter of claim 14 wherein the first load comprises a first inductor, the second load comprises a second inductor, and the transconductance is a PMOS device. 20. The transmitter of claim 14 further comprising: a power amplifier having an input terminal coupled to the first terminal of the converter circuit; and a mixer having output terminals coupled to the first terminal and the second terminal of the converter circuit. 21. The transmitter of claim 18 wherein the NMOS device is a native device. 22. The transmitter of claim 18 wherein the NMOS device is formed in a bulk region coupled to a source terminal of the NMOS device. 23. The transmitter of claim 18 wherein the NMOS device is biased by a current source. 24. The transmitter of claim 23 wherein the current source is a common-source configured NMOS device. 25. A transceiver comprising: a receiver circuit coupled to a transmitter, the transmitter comprising: a converter circuit having a first terminal configured to receive a first current and provide an output voltage and a second terminal configured to receive a second current, the converter circuit comprising: a first load, coupled between a third terminal and the second terminal, and configured to convert the second current to a first voltage; a transconductance, coupled to the second terminal and the first terminal, and configured to convert the first voltage to a third current; and a second load, coupled between a fourth terminal and the first terminal and configured to convert a sum of the first current and the third current to the output voltage; a power amplifier having an input terminal coupled to the first terminal of the converter circuit; and a mixer having output terminals coupled to the first terminal and the second terminal of the converter circuit, wherein the third current is approximately inversely proportional to the first voltage, and wherein the third terminal and fourth terminal are coupled together and configured to receive a first reference voltage. 26. An electronic system comprising a transceiver coupled to an interface bus, the electronic system being capable of wireless data communication with another electronic system via the transceiver, the transceiver comprising: a receiver circuit coupled to a transmitter, the transmitter comprising: a converter circuit having a first terminal configured to receive a first current and provide an output voltage, and a second terminal configured to receive a second current, the converter circuit comprising: a first load, coupled between a third terminal and the second terminal, and configured to convert the second current to a first voltage; a transconductance, coupled to the second terminal and the first terminal, and configured to convert the first voltage to a third current; and a second load, coupled between a fourth terminal and the first terminal, and configured to convert a sum of the first current and the third current to the output voltage; a power amplifier having an input terminal coupled to the first terminal of the converter circuit; and a mixer having output terminals coupled to the first terminal and the second terminal of the converter circuit, wherein the third current is approximately inversely proportional to the first voltage, and wherein the third terminal and fourth terminal are coupled together and configured to receive a first reference voltage. 27. A converter circuit comprising: a first inductor coupled between a first terminal receiving a first current signal and a second terminal; a second inductor coupled between a third terminal receiving a second current signal and a fourth terminal; and a first transistor coupled between the third terminal and a fifth terminal, having a control electrode coupled to the first terminal, wherein the first current signal and the second current signal form a differential current signal, and
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