초록 ▼

A double firewalled system is disclosed for protecting remote enterprise servers that provide communication services to telecommunication network customers from unauthorized third parties. A first router directs all connection requests to one or more secure web servers, which may utilize a load bala

A double firewalled system is disclosed for protecting remote enterprise servers that provide communication services to telecommunication network customers from unauthorized third parties. A first router directs all connection requests to one or more secure web servers, which may utilize a load balancer to efficiently distribute the session connection load among a high number of authorized client users. On the network side of the web servers, a second router directs all connection requests to a dispatcher server, which routes application server calls to a proxy server for the application requested. A plurality of data security protocols are also employed. The protocols provide for an identification of the user, and an authentication of the user to ensure the user is who he/she claims to be and a determination of entitlements that the user may avail themselves of within the enterprise system. Session security is described, particularly as to the differences between a remote user's copper wire connection to a legacy system and a user's remote connection to the enterprise system over a "stateless"public Internet, where each session is a single transmission, rather than an interval of time between logon and logoff, as is customary in legacy systems.

대표청구항 ▼

A double firewalled system is disclosed for protecting remote enterprise servers that provide communication services to telecommunication network customers from unauthorized third parties. A first router directs all connection requests to one or more secure web servers, which may utilize a load bala

A double firewalled system is disclosed for protecting remote enterprise servers that provide communication services to telecommunication network customers from unauthorized third parties. A first router directs all connection requests to one or more secure web servers, which may utilize a load balancer to efficiently distribute the session connection load among a high number of authorized client users. On the network side of the web servers, a second router directs all connection requests to a dispatcher server, which routes application server calls to a proxy server for the application requested. A plurality of data security protocols are also employed. The protocols provide for an identification of the user, and an authentication of the user to ensure the user is who he/she claims to be and a determination of entitlements that the user may avail themselves of within the enterprise system. Session security is described, particularly as to the differences between a remote user's copper wire connection to a legacy system and a user's remote connection to the enterprise system over a "stateless"public Internet, where each session is a single transmission, rather than an interval of time between logon and logoff, as is customary in legacy systems. operand data request signal, and said burst transfer signal are all transmitted. 2. The micro-processor as set forth in claim 1, further comprising: (f) a first register storing a condition at which burst transfer of a command fetch is completed; and (g) a first comparator receiving the next command fetch address and said condition transmitted from said first register to thereby detect a boundary condition of a memory, and transmitting a first signal indicating that burst transfer should be completed, as a result of detecting said boundary condition, said access priority judging circuit making judgement as to whether a command fetch access should be taken preference over an operand data access in the next bus access in accordance with said first signal, when data stored in said access register is a command fetch access, and said pre-fetch request signal, said operand data request signal, and said burst transfer signal are all transmitted. 3. The micro-processor as set forth in claim 1, further comprising: (h) a first counter counting the number of burst transfer; (i) a second register storing the number of burst transfer in a command fetch; and (j) a second comparator comparing said number of burst transfer counted by said first counter to said number of burst transfer stored in said second register, and transmitting a second signal indicating that burst transfer should be completed, as a result of comparison, said access priority judging circuit making judgement as to whether a command fetch access should be taken preference over an operand data access in the next bus access in accordance with said second signal, when data stored in said access register is a command fetch access, and said pre-fetch request signal, said operand data request signal, and said burst transfer signal are all transmitted. 4. The micro-processor as set forth in claim 1, further comprising: (k) a detector detecting that a command code in said pre-fetch queue FIFO is smaller than a predetermined amount, on the basis of said pre-fetch queue valid, and transmitting a third signal indicating that burst transfer should be completed, as a result of detection, said access priority judging circuit making judgement as to whether a command fetch access should be taken preference over an operand data access in the next bus access in accordance with said third signal, when data stored in said access register is a command fetch access, and said pre-fetch request signal, said operand data request signal, and said burst transfer signal are all transmitted. 5. The micro-processor as set forth in claim 1, further comprising: (l) a second counter counting the number of burst transfer; (m) a third register storing the number of burst transfer in operand data access; and (n) a third comparator comparing said number of burst transfer counted by said second counter to said number of burst transfer stored in said third register, and transmitting a fourth signal indicating that burst transfer should be completed, as a result of comparison, said access priority judging circuit giving first priority to said queue empty signal, second priority to said operand data request signal, and third priority to said pre-fetch request signal, respectively, said access priority judging circuit making judgement as to whether an operand data access should be taken preference over a command fetch access in the next bus access in accordance with said fourth signal, when data stored in said access register is an operand data access, and said queue empty signal, said operand data request signal, and said burst transfer signal are all transmitted. 6. The micro-processor as set forth in claim 1, further comprising: (o) a fourth register storing a condition at which burst transfer in operand data is completed; and (p) a fourth comparator receiving the next operand data address and said condition transmitted from said fourth register to thereby detect a bo undary condition of a memory, and transmitting a fifth signal indicating that burst transfer should be completed, as a result of detecting said boundary condition, said access priority judging circuit giving first priority to said queue empty signal, second priority to said operand data request signal, and third priority to said pre-fetch request signal, respectively, said access priority judging circuit making judgement that the next bus address is operand data access in accordance with said fifth signal, when data stored in said access register is an operand data access, and said queue empty signal, said operand data request signal, and said burst transfer signal are all transmitted. 7. A micro-processor comprising: (a) a bus interface in which a request of operand data is given a higher priority than a request of command fetch; (b) an access register storing data about the previous access, said micro-processor, if a request of operand data is made while burst transfer access for command fetch is being carried out, determining whether burst transfer should be interrupted or continued, based on data stored in said access register, wherein said micro-processor takes command fetch in preference to over operand data access, while a first signal is being transmitted which first signal indicates that a memory is put in such a condition that burst transfer of the next access can be carried out. 8. A micro-processor comprising: (a) a bus interface in which a request of operand data is given a higher priority than a request of command fetch; (b) an access register storing data about the previous access, said micro-processor, if a request of operand data is made while burst transfer access for command fetch is being carried out, taking command fetch access in preference to operand data access until a first or second signal is transmitted, said first signal indicating that a memory is put in such a condition that burst transfer of the next access can be carried out, said second signal indicating that burst transfer should be completed. 9. A micro-processor comprising: (a) a bus interface in which a request of operand data is given a higher priority than a request of command fetch; (b) an access register storing data about the previous access, said micro-processor, if a request of operand data is made while burst transfer access for command fetch is being carried out, taking command fetch access in preference to operand data access when first and second signals are transmitted, said first signal indicating that a memory is put in such a condition that burst transfer of the next access can be carried out, said second signal indicating that burst transfer should be completed. 10. A method of driving a micro-processor, comprising the step of taking command fetch access in preference to operand data access in the next bus access, when the following conditions are all fulfilled: (a) the previous bus access is command fetch access; (b) there is vacancy in pre-fetch queue FIFO; (c) there is generated operand data access; and (d) a memory is in such a condition that burst transfer can be carried out. 11. A method of driving a micro-processor, comprising the steps of (a) storing a condition at which burst transfer of command fetch is completed; (b) detecting a boundary condition of a memory, based on the next command fetch address and said condition; and (c) judging whether command fetch access should be taken preference over operand data access in the next bus access in accordance with a result of detection carried out in said step (b), when the following conditions are all fulfilled: (c1) the previous bus access is command fetch access; (c2) there is vacancy in pre-fetch queue FIFO; (c3) there is generated operand data access; and (c4) a memory is in such a condition that burst transfer can be carried out. 12. A method of driving a micro-processor, comprising the steps of (a) counting the