$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Double gate semiconductor device having separate gates 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/76
  • H01L-029/94
  • H01L-031/062
  • H01L-031/113
출원번호 US-0290158 (2002-11-08)
발명자 / 주소
  • Ahmed, Shibly S.
  • Wang, Haihong
  • Yu, Bin
출원인 / 주소
  • Advanced Micro Devices, Inc.
대리인 / 주소
    Harrity & Snyder, LLP
인용정보 피인용 횟수 : 148  인용 특허 : 3

초록

A semiconductor device may include a substrate and an insulating layer formed on the subtrate. A fin may be formed on the insulating layer and may include a number of side surfaces and a top surface. A first gate may be formed on the insulating layer proximate to one of the number of side surfaces o

대표청구항

1. A semiconductor device, comprising: a substrate; an insulating layer formed on the substrate; a fin formed on the insulating layer and including a plurality of side surfaces and a top surface; a first gate formed on the insulating layer proximate to one of plurality of side surfaces of the

이 특허에 인용된 특허 (3)

  1. Tsuji Kazuhiko (Nara JPX), High density integrated semiconductor device.
  2. Zoran Krivokapic ; Matthew Buynoski, Self-aligned double gate silicon-on-insulator (SOI) device.
  3. Leonard Forbes ; Wendell P. Noble ; Alan R. Reinberg, Vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk, SOI and thin film structures and method of forming same.

이 특허를 인용한 특허 (148)

  1. Kavalieros,Jack T.; Shah,Uday; Rachmady,Willy; Doyle,Brian S., Apparatus and method for selectively recessing spacers on multi-gate devices.
  2. Anderson,Brent A.; Nowak,Edward J., Back gate FinFET SRAM.
  3. Anderson,Brent A.; Nowak,Edward J., Back gate FinFET SRAM.
  4. Radosavljevic,Marko; Majumdar,Amlan; Doyle,Brian S.; Kavalieros,Jack; Doczy,Mark L.; Brask,Justin K.; Shah,Uday; Datta,Suman; Chau,Robert S., Block contact architectures for nanoscale channel transistors.
  5. Lindert, Nick; Cea, Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
  6. Lindert,Nick; Cea,Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
  7. Lindert,Nick; Cea,Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
  8. Doyle, Brian S.; Jin, Been-Yih; Kavalieros, Jack T.; Datta, Suman; Brask, Justin K.; Chau, Robert S., CMOS devices with a single work function gate electrode and method of fabrication.
  9. Chan, Philip Ching Ho; Chan, Man Sun; Wu, Xusheng; Zhang, Shengdong, Complementary metal-oxide-semiconductor transistor structure for high density and high performance integrated circuits.
  10. Brask, Justin K.; Datta, Suman; Doczy, Mark L.; Blackwell, James M.; Metz, Matthew V.; Kavalieros, Jack T.; Chau, Robert S., Dielectric interface for group III-V semiconductor device.
  11. Yeo, Yee-Chia; Wang, Ping-Wei; Chen, Hao-Yu; Yang, Fu-Liang; Hu, Chenming, Doping of semiconductor fin devices.
  12. Yeo, Yee-Chia; Wang, Ping-Wei; Chen, Hao-Yu; Yang, Fu-Liang; Hu, Chenming, Doping of semiconductor fin devices.
  13. Yeo, Yee-Chia; Wang, Ping-Wei; Chen, Hao-Yu; Yang, Fu-Liang; Hu, Chenming, Doping of semiconductor fin devices.
  14. Yeo,Yee Chia; Wang,Ping Wei; Chen,Hao Yu; Yang,Fu Liang; Hu,Chenming, Doping of semiconductor fin devices.
  15. Anderson, Brent A.; Nowak, Edward J., Double gate isolation.
  16. Anderson,Brent A.; Nowak,Edward J., Double gate isolation.
  17. Yu, Bin; Ahmed, Shibly S.; Wang, Haihong, Double-gate semiconductor device with gate contacts formed adjacent sidewalls of a fin.
  18. Van Dal, Mark; Surdeanu, Radu, Double-gate semiconductor devices having gates with different work functions and methods of manufacture thereof.
  19. Achuthan, Krishnashree; Ahmed, Shibly S.; Wang, Haihong; Yu, Bin, Dual silicon layer for chemical mechanical polishing planarization.
  20. Achuthan, Krishnashree; Ahmed, Shibly S.; Wang, Haihong; Yu, Bin, Dual silicon layer for chemical mechanical polishing planarization.
  21. Achuthan,Krishnashree; Ahmed,Shibly S.; Wang,Haihong; Yu,Bin, Dual silicon layer for chemical mechanical polishing planarization.
  22. Kavalieros, Jack T.; Mukherjee, Niloy; Dewey, Gilbert; Somasekhar, Dinesh; Doyle, Brian S., Embedded memory cell and method of manufacturing same.
  23. Radosavljevic, Marko; Datta, Suman; Doyle, Brian S.; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Majumdar, Amian; Chau, Robert S., Field effect transistor with metal source/drain regions.
  24. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  25. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  26. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  27. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  28. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  29. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  30. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  31. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  32. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  33. Oh, Chang-Woo; Park, Dong-Gun; Kim, Dong-Won; Lee, Yong-Kyu, Fin field effect transistors including oxidation barrier layers.
  34. Lin, Ming-Ren; Goo, Jung-Suk; Wang, Haihong; Xiang, Qi, FinFET device incorporating strained silicon in the channel region.
  35. Cheng, Kangguo; Doris, Bruce B.; Khakifirooz, Ali; Kulkarni, Pranita, FinFET non-volatile memory and method of fabrication.
  36. Erickson, Karl R.; Paone, Phil C.; Paulsen, David P.; Sheets, II, John E.; Uhlmann, Gregory J.; Williams, Kelly L., FinFET with body contact.
  37. Sonsky, Jan; Surdeanu, Radu, FinFET with separate gates and method for fabricating a finFET with separate gates.
  38. Lin, Ming-Ren; Maszara, Witold P.; Wang, Haihong; Yu, Bin, Fully silicided gate structure for FinFET devices.
  39. An, Judy Xilin; Krivokapic, Zoran; Wang, Haihong; Yu, Bin, Germanium MOSFET devices and methods for making same.
  40. An, Judy Xilin; Krivokapic, Zoran; Wang, Haihong; Yu, Bin, Germanium MOSFET devices and methods for making same.
  41. An,Judy Xilin; Krivokapic,Zoran; Wang,Haihong; Yu,Bin, Germanium MOSFET devices and methods for making same.
  42. Shaheen,Mohamad A.; Doyle,Brian; Dutta,Suman; Chau,Robert S.; Tolchinsky,Peter, High mobility tri-gate devices and methods of fabrication.
  43. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors.
  44. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
  45. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
  46. Chang,Peter L. D.; Doyle,Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
  47. Maly, Wojciech P., Integrated circuit device, system, and method of fabrication.
  48. Maly, Wojciech P., Integrated circuit device, system, and method of fabrication.
  49. Chang, Peter L. D., Integration of planar and tri-gate devices on the same substrate.
  50. Chang,Peter L. D., Integration of planar and tri-gate devices on the same substrate.
  51. Chien, Wei-Ting Kary; Yang, Siyuan, Knowledge-based statistical method and system to determine reliability compatibility for semiconductor integrated circuits.
  52. Datta,Suman; Brask,Justin K.; Kavalieros,Jack; Doyle,Brian S.; Dewey,Gilbert; Doczy,Mark L.; Chau,Robert S., Lateral undercut of metal gate in SOI device.
  53. Maly, Wojciech P., Lithography and associated methods, devices, and systems.
  54. Datta,Suman; Doyle,Brian S.; Chau,Robert S.; Kavalieros,Jack; Zheng,Bo; Hareland,Scott A., Method and apparatus for improving stability of a 6T CMOS SRAM cell.
  55. Doris, Bruce B.; Boyd, Diane C.; Zhu, Huilong, Method and structure for strained FinFET devices.
  56. Cheng, Kangguo; Doris, Bruce B.; Furukawa, Toshiharu, Method for double pattern density.
  57. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  58. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  59. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  60. Yu, Bin; An, Judy Xilin; Dakshina-Murthy, Srikanteswara, Method for forming a gate in a FinFET device.
  61. Shah,Uday; Doyle,Brian S.; Brask,Justin K.; Chau,Robert S., Method of fabricating a multi-cornered film.
  62. Brask,Justin K.; Doyle,Brian S.; Kavalleros,Jack; Doczy,Mark; Shah,Uday; Chau,Robert S., Method of forming a metal oxide dielectric.
  63. Brask, Justin K.; Doyle, Brian S.; Kavalieros, Jack; Doczy, Mark; Shah, Uday; Chau, Robert S., Method of forming metal gate electrodes using sacrificial gate electrode material and sacrificial gate dielectric material.
  64. Doyle,Brian S.; Datta,Suman; Kavalieros,Jack T.; Majumdar,Amlan, Method of ion implanting for tri-gate devices.
  65. Zhu, Huilong; Doris, Bruce B.; Wang, Xinlin; Beintner, Jochen; Zhang, Ying; Oldiges, Philip J., Method of making double-gated self-aligned finFET having gates of different lengths.
  66. Chidambarrao,Dureseti; Dokumaci,Omer, Method of manufacture of FinFET devices with T-shaped fins and devices manufactured thereby.
  67. Luo, Zhijiong; Chong, Yung Fu; Zhu, Huilong, Method of manufacturing a semiconductor structure.
  68. Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Chau, Robert S., Method of patterning a film.
  69. Zhu,Huilong; Doris,Bruce B., Methods for manufacturing a finFET using a conventional wafer and apparatus manufactured therefrom.
  70. Zhu, Huilong; Doris, Bruce B., Methods for manufacturing a finfet using a conventional wafer and apparatus manufactured therefrom.
  71. Brask, Justin K.; Kavalieros, Jack; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S.; Doyle, Brian S., Methods for patterning a semiconductor film.
  72. Oh,Chang Woo; Park,Dong Gun; Kim,Dong Won; Lee,Yong Kyu, Methods of forming fin field effect transistors using oxidation barrier layers.
  73. Zhang,Yuegang; Doyle,Brian S.; Bourianoff,George I., Multi-gate carbon nano-tube transistors.
  74. Kavalieros, Jack T.; Brask, Justin K.; Datta, Suman; Doyle, Brian S.; Chau, Robert S., Multigate device with recessed strain regions.
  75. Doyle, Brian S.; Datta, Suman; Jin, Been Yih; Chau, Robert, Non-planar MOS structure with a strained channel region.
  76. Doyle,Brian S.; Datta,Suman; Jin,Been Yih; Chau,Robert, Non-planar MOS structure with a strained channel region.
  77. Brask,Justin K.; Kavalieros,Jack T.; Doyle,Brian S.; Chau,Robert S., Non-planar microelectronic device having isolation element to mitigate fringe effects and method to fabricate same.
  78. Doyle,Brian S; Datta,Suman; Jin,Been Yih; Zelick,Nancy M; Chau,Robert, Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow.
  79. Hareland,Scott A.; Chau,Robert S.; Doyle,Brian S.; Datta,Suman; Jin,Been Yih, Nonplanar device with stress incorporation layer and method of fabrication.
  80. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  81. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  82. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  83. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  84. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  85. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  86. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  87. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
  88. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
  89. Hareland,Scott A.; Chau,Robert S.; Doyle,Brian S.; Rios,Rafael; Linton,Tom; Datta,Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
  90. Brask, Justin K.; Dovle, Brian S.; Kavalleros, Jack; Doczy, Mark; Shah, Uday; Chau, Robert S., Nonplanar transistors with metal gate electrodes.
  91. Brask,Justin K.; Doyle,Brian S.; Doczy,Mark L.; Chau,Robert S., Nonplanar transistors with metal gate electrodes.
  92. Brask,Justin K.; Doyle,Brian S.; Doczy,Mark L.; Chau,Robert S., Nonplanar transistors with metal gate electrodes.
  93. Brask,Justin K.; Doyle,Brian S.; Kavalieros,Jack; Doczy,Mark; Shah,Uday; Chau,Robert S., Nonplanar transistors with metal gate electrodes.
  94. Ahmed,Shibly S.; Tabery,Cyrus E.; Yu,Bin, Planarizing sacrificial oxide to improve gate critical dimension in semiconductor devices.
  95. Erickson, Karl R.; Paone, Phil C.; Paulsen, David P.; Sheets, John E.; Uhlmann, Gregory J.; Williams, Kelly L., Plural differential pair employing FinFET structure.
  96. Kavalieros, Jack T.; Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Datta, Suman; Doczy, Mark L.; Metz, Matthew V.; Chau, Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
  97. Kavalieros,Jack T.; Brask,Justin K.; Doyle,Brian S.; Shah,Uday; Datta,Suman; Doczy,Mark L.; Metz,Matthew V.; Chau,Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
  98. Rachmady, Willy; Shah, Uday; Kavalieros, Jack T.; Doyle, Brian S., Selective anisotropic wet etching of workfunction metal for semiconductor devices.
  99. Cohen,Guy M.; Wong,Hon Sum P., Self-aligned double gate mosfet with separate gates.
  100. Okano, Kimitoshi, Semiconductor device and method of fabricating the same.
  101. Anderson, Brent A.; Nowak, Edward J.; Rainey, BethAnn, Semiconductor device having freestanding semiconductor layer.
  102. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  103. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  104. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  105. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  106. Oh, Chang-woo; Park, Dong-gun; Kim, Dong-won; Suk, Sung-dae, Semiconductor devices including channel and junction regions of different semiconductor materials.
  107. Oh, Chang-woo; Park, Dong-gun; Kim, Dong-won; Suk, Sung-dae, Semiconductor devices including fin shaped semiconductor regions and stress inducing layers.
  108. Oh,Chang woo; Park,Dong gun; Kim,Dong won; Suk,Sung dae, Semiconductor devices including stress inducing layers.
  109. Chen,Hung Wei; Yeo,Yee Chia; Lee,Di Hong; Yang,Fu Liang; Hu,Chenming, Semiconductor nano-wire devices and methods of fabrication.
  110. Ngo,Minh V.; Besser,Paul R.; Lin,Ming Ren; Wang,Haihong, Semiconductor with tensile strained substrate and method of making the same.
  111. Yeo, Yee-Chia; Yang, Fu-Liang; Hu, Chenming, Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors.
  112. Yeo,Yee Chia; Yang,Fu Liang; Hu,Chenming, Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors.
  113. Yang,Chih Yuh; Ahmed,Shibly S.; Dakshina Murhty,Srikanteswara; Tabery,Cyrus E.; Yu,Bin, Source and drain protection and stringer-free gate formation in semiconductor devices.
  114. Ching, Kuo-Cheng; Liu, Chi-Wen, Source/drain regions for fin field effect transistors and methods of forming same.
  115. Ching, Kuo-Cheng; Liu, Chi-Wen, Source/drain regions for fin field effect transistors and methods of forming same.
  116. Doyle,Brian S; Rakshit,Titash; Chau,Robert S; Datta,Suman; Brask,Justin K; Shah,Uday, Stacked multi-gate transistor design and method of fabrication.
  117. Hudait, Mantu K.; Shaheen, Mohamad A.; Chow, Loren A.; Tolchinsky, Peter G.; Fastenau, Joel M.; Loubychev, Dmitri; Liu, Amy W. K., Stacking fault and twin blocking barrier for integrating III-V on Si.
  118. Dakshina-Murthy, Srikanteswara; An, Judy Xilin; Krivokapic, Zoran; Wang, Haihong; Yu, Bin, Strained channel FinFET.
  119. Dakshina-Murthy, Srikanteswara; An, Judy Xilin; Krivokapic, Zoran; Wang, Haihong; Yu, Bin, Strained channel finfet.
  120. Huang, Yi-Chun; Wang, Yen-Ping; Ko, Chih-Hsin, Strained channel transistor formation.
  121. Cohen, Guy Moshe, Strained-channel fin field effect transistor (FET) with a uniform channel thickness and separate gates.
  122. Yeo, Yee-Chia; Yang, Fu-Liang; Hu, Chenming, Strained-channel multiple-gate transistor.
  123. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  124. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  125. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  126. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  127. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  128. Yeo,Yee Chia; Yang,Fu Liang, Structure and method for forming the gate electrode in a multiple-gate transistor.
  129. Yeo,Yee Chia; Yang,Fu Liang, Structure and method for forming the gate electrode in a multiple-gate transistor.
  130. Zhu,Huilong; Doris,Bruce B.; Wang,Xinlin; Beintner,Jochen; Zhang,Ying; Oldiges,Philip J., Structure and method of making double-gated self-aligned finFET having gates of different lengths.
  131. Zhu,Huilong; Doris,Bruce B., Structure and method of manufacturing a finFET device having stacked fins.
  132. Anderson, Brent A.; Breitwisch, Matthew J.; Nowak, Edward J., Substrate backgate for trigate FET.
  133. Anderson,Brent A.; Breitwisch,Matthew J.; Nowak,Edward J., Substrate backgate for trigate FET.
  134. Doyle, Brian S.; Jin, Been-Yih; Kavalieros, Jack T.; Datta, Suman, Substrate band gap engineered multi-gate pMOS devices.
  135. Ngo, Minh V.; Besser, Paul R.; Lin, Ming Ren; Wang, Haihong, Tensile strained substrate.
  136. Anderson, Brent A.; Nowak, Edward J., Three-mask method of constructing the final hard mask used for etching the silicon fins for FinFETs.
  137. Chau, Robert S.; Doyle, Brian S.; Kavalieros, Jack; Barlage, Douglas; Datta, Suman, Tri-gate devices and methods of fabrication.
  138. Chau, Robert S.; Doyle, Brian S.; Kavalieros, Jack; Barlage, Douglas; Datta, Suman; Hareland, Scott A., Tri-gate devices and methods of fabrication.
  139. Chau, Robert S.; Doyle, Brian S.; Kavalieros, Jack; Barlage, Douglas; Datta, Suman; Hareland, Scott A., Tri-gate devices and methods of fabrication.
  140. Chau,Robert S.; Doyle,Brian S.; Kavalieros,Jack; Barlage,Douglas; Datta,Suman, Tri-gate devices and methods of fabrication.
  141. Chau,Robert S.; Doyle,Brian S.; Kavalieros,Jack; Barlage,Douglas; Datta,Suman, Tri-gate devices and methods of fabrication.
  142. Chau,Robert S.; Doyle,Brian S.; Kavalieros,Jack; Barlage,Douglas; Datta,Suman; Hareland,Scott A., Tri-gate devices and methods of fabrication.
  143. Ban,Ibrahim; Chang,Peter L. D., Tri-gate integration with embedded floating body memory cell using a high-K dual metal gate.
  144. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
  145. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
  146. Chau,Robert; Datta,Suman; Doyle,Brian S; Jin,Been Yih, Tri-gate transistors and methods to fabricate same.
  147. Shaheen, Mohamad A.; Rachmady, Willy; Tolchinsky, Peter, Ultra-thin oxide bonding for S1 to S1 dual orientation bonding.
  148. Metz,Matthew V.; Datta,Suman; Doczy,Mark L.; Kavalieros,Jack T.; Brask,Justin K.; Chau,Robert S., Uniform silicide metal on epitaxially grown source and drain regions of three-dimensional transistors.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로