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Leadless flip chip carrier design and structure 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/10
  • H01L-023/48
출원번호 US-0877912 (2001-06-08)
발명자 / 주소
  • Hashemi, Hassan S.
출원인 / 주소
  • Skyworks Solutions, Inc.
대리인 / 주소
    Farjami & Farjami LLP
인용정보 피인용 횟수 : 27  인용 특허 : 23

초록

One disclosed embodiment comprises a substrate having a top surface for receiving a semiconductor die with a number of solder bumps on its active surface. The disclosed embodiment further comprises a printed circuit board attached to a bottom surface of the substrate. Another disclosed embodiment co

대표청구항

1. A structure comprising: a substrate having a top surface for receiving a die having a plurality of solder bumps on an active surface of said die; a heat spreader situated on a bottom surface of said substrate; a printed circuit board attached to said bottom surface of said substrate, said he

이 특허에 인용된 특허 (23)

  1. Weber Bernd,DEX ; Hofsaess Dietmar,DEX ; Butschkau Werner,DEX ; Dittrich Thomas,DEX ; Schiefer Peter,DEX, Arrangement including a substrate for power components and a heat sink, and a method for manufacturing the arrangement.
  2. Selna Erich (Mountain View CA), Ball grid array package for a integrated circuit.
  3. Herandez Jorge M. (1920 E. Jarvis Mesa AZ 85202) Simpson Scott S. (Senexet Rd. Woodstock CT 06281) Hyslop Michael S. (4147 W. Victoria La. Chandler AZ 85226), Device for interconnecting integrated circuit packages to circuit boards.
  4. Ference Thomas G. ; Howell Wayne J. ; Sprogis Edmund J., Dual chip with heat sink.
  5. Celaya Phillip C. ; Kerr John R., Electronic component assembly having an encapsulation material and method of forming the same.
  6. Yamamoto Toshio,JPX ; Hirachi Yasutake,JPX, Hermetically sealed semiconductor module composed of semiconductor integrated circuit and antenna element.
  7. Palmer Mark J., Integrated circuit package with a plurality of vias that are electrically connected to an internal ground plane and ther.
  8. Gaul Stephen Joseph, Intergrated circuit with coaxial isolation and method.
  9. Hashemi Hassan S., Leadless chip carrier design and structure.
  10. Lau John H., Low-cost surface-mount compatible land-grid array (LGA) chip scale package (CSP) for packaging solder-bumped flip chips.
  11. Houghton Christopher Lee ; Brench Colin Edward, Method and system for controlling radio frequency radiation in microelectronic packages using heat dissipation structures.
  12. Beilstein ; Jr. Kenneth Edward ; Bertin Claude Louis ; Cronin John Edward ; Howell Wayne John ; Leas James Marc ; Perlman David Jacob, Method and workpiece for connecting a thin layer to a monolithic electronic modules surface and associated module pack.
  13. Miyagi Takeshi (Fujisawa JPX) Matsumoto Kazuhiro (Yokohama JPX) Sasaki Tomiya (Yokohama JPX) Iwasaki Hideo (Kawasaki JPX) Hisano Katsumi (Yokohama JPX), Multi-layer substrate.
  14. Katchmar Roman (Ottawa CAX), Printed circuit board and heat sink arrangement.
  15. Tseng Tzyy-Jang,TWX ; Cheng David C. H.,TWX ; Lao Shaw-Wen,TWX, Printed circuit board with thermal conductive structure.
  16. Inoue Kazuaki,JPX ; Yamashita Hiroyuki,JPX ; Nakamura Norio,JPX ; Yoda Hiroyuki,JPX, Semiconductor device for heat discharge.
  17. Higgins ; III Leo M., Semiconductor device having a sub-chip-scale package structure and method for forming same.
  18. Gaku Morio,JPX ; Ikeguchi Nobuyuki,JPX ; Kobayashi Toshihiko,JPX, Semiconductor plastic package, metal plate for said package, and method of producing copper-clad board for said package.
  19. Gaku Morio,JPX ; Ikeguchi Nobuyuki,JPX ; Kobayashi Toshihiko,JPX, Semiconductor plastic package, metal plate for said package, and method of producing copper-clad board for said package.
  20. Maley Reading G., Stacked multi-chip modules using C4 interconnect technology having improved thermal management.
  21. Yoshida Yuichi,JPX, Stacked semiconductor device.
  22. Ahn Kie Y. ; Forbes Leonard ; Cloud Eugene H., Structure and method for a high performance electronic packaging assembly.
  23. Kevin Kwong-Tai Chung, Tamper-resistant wireless article including an antenna.

이 특허를 인용한 특허 (27)

  1. Ho, Chien-Hung; Lee, Chiu-Min; Kuo, Chen-Shen, Ceramic substrate and semiconductor package having the same.
  2. Lee, Jae-Seok, Circuit board and method of manufacturing the same.
  3. Sauerbier, Juergen; Gruebl, Wolfgang; Schuch, Bernhard; Trageser, Hubert; Robin, Hermann-Josef, Circuit board having a plurality of circuit board layers arranged one over the other having bare die mounting for use as a gearbox controller.
  4. Divakar, Mysore Purushotham; Keating, David; Russell, Antoin, DC-DC converter implemented in a land grid array package.
  5. Divakar,Mysore Purushotham; Keating,David; Russell,Antoin, DC-DC converter implemented in a land grid array package.
  6. Yokota, Yasuo; Ogura, Motonari; Hirata, Masahiko, Electric circuit board.
  7. Tomuta, Daniela Georgeta; Meinen, Albert Hendrik Jan; Ruiter, Gezinus; Van Spijker, Jan, Electron bombarded image sensor array device and its manufacturing method.
  8. Kuan, Heap Hoe; Huang, Rui; Lin, Yaojian; Chow, Seng Guan, Encapsulant interposer system with integrated passive devices and manufacturing method therefor.
  9. Kuan, Heap Hoe; Huang, Rui; Lin, Yaojian; Chow, Seng Guan, Encapsulant interposer system with integrated passive devices and manufacturing method therefor.
  10. Liu, Yong, Flexible and stackable semiconductor die packages having thin patterned conductive layers.
  11. Lange, Bernhard P; Coyle, Anthony L, Flip chip package with advanced electrical and thermal properties for high current designs.
  12. Farnworth, Warren M., Interconnect and method for mounting an electronic device to a substrate.
  13. Hashemi, Hassan S., Leadless chip carrier design and structure.
  14. Heinz, Helmut; Schuch, Bernhard, Method for producing circuit arrangments.
  15. Hasegawa, Hidenori, Method of manufacturing a stacked semiconductor device.
  16. Hsiao, Shu-Wei, Printed circuit board structure with heat dissipation function.
  17. Sano, Hikari; Tomita, Yoshihiro; Nakano, Takahiro, Semiconductor chip and semiconductor device.
  18. Nakagawa, Tomokatsu; Chikawa, Yasunori; Rai, Akiteru; Katoh, Tatsuya; Sugiyama, Takuya, Semiconductor device and display apparatus.
  19. Kawano, Masaya, Semiconductor device having a through electrode.
  20. Kawano, Masaya, Semiconductor device having a through electrode.
  21. Hasegawa,Hidenori, Semiconductor device with stacked chips.
  22. Miyasaka,Hideo, Semiconductor device, its manufacturing method, circuit board, and electronic unit.
  23. Reisner, Russ, Semiconductor die with backside passive device integration.
  24. Choi, Soung-yong; Park, Min-hyo, Semiconductor package form within an encapsulation.
  25. Choi, Seung-yong; Park, Min-hyo, Semiconductor package formed within an encapsulation.
  26. Fukushima, Hiroyuki; Kumokawa, Fumio, Wiring board.
  27. Denda, Tatsuaki; Kobayashi, Kazutaka, Wiring substrate and semiconductor package.
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