초록 ▼

A system is provided for detecting blockage of an automotive side object detection system ("SODS"). The system includes a blockage detection processor, which is operative to determine whether an RF leakage signal level sensed between transmit and receive antennas of the system substantially match on

A system is provided for detecting blockage of an automotive side object detection system ("SODS"). The system includes a blockage detection processor, which is operative to determine whether an RF leakage signal level sensed between transmit and receive antennas of the system substantially match one or more of a plurality of pattern recognition information curves. If it is determined that the leakage signal level substantially matches one or more of a plurality of pattern recognition information curves, a blocked condition of the SODS is declared, as may be caused by mud, salt, ice, etc. The blockage detection processor is further operative to determine whether the leakage signal exceeds a predetermined blockage threshold level. If the leakage exceeds the predetermined blockage threshold level, a blocked condition of the SODS is also declared.

대표청구항 ▼

A system is provided for detecting blockage of an automotive side object detection system ("SODS"). The system includes a blockage detection processor, which is operative to determine whether an RF leakage signal level sensed between transmit and receive antennas of the system substantially match on

A system is provided for detecting blockage of an automotive side object detection system ("SODS"). The system includes a blockage detection processor, which is operative to determine whether an RF leakage signal level sensed between transmit and receive antennas of the system substantially match one or more of a plurality of pattern recognition information curves. If it is determined that the leakage signal level substantially matches one or more of a plurality of pattern recognition information curves, a blocked condition of the SODS is declared, as may be caused by mud, salt, ice, etc. The blockage detection processor is further operative to determine whether the leakage signal exceeds a predetermined blockage threshold level. If the leakage exceeds the predetermined blockage threshold level, a blocked condition of the SODS is also declared. ock signal of a second clock phase; iii. a first data terminal adapted to receive a first series of data bits; iv. a second data terminal adapted to receive a second series of data bits synchronized with the first series of data bits so that pairs of data bits arrive at the first and second data terminals substantially simultaneously and v. a first data output terminal; vi. wherein the current-steering circuit is adapted to combine the first and second series of data bits into a third series of data bits and to provide the third series of data bits on the first data output terminal; b. a current source connected to the first data output terminal; c. a second current-steering circuit including: i. a third clock terminal connected to the first clock terminal; ii. a fourth clock terminal connected to the second clock terminal; iii. a third data terminal adapted to receive a fourth series of data bits complementary to the first series of data bits; and iv. a second data output terminal adapted to receive a fifth series of data bits complementary to the second series of data bits; vi. wherein the second current-steering circuit is adapted to combine the fourth and fifth series of data bits into a sixth series of data bits complementary to the third series of data bits and to provide the sixth series of data bits on the second data output terminal; and d. a second current source connected to the second data output terminal. 8. The data combiner of claim 7, wherein the current-steering circuit further includes: a. a first inverter having a first-inverter input terminal connected to the first data terminal and a first-inverter output terminal connected to the first data output terminal; b. a second inverter having a second-inverter input terminal connected to the second data terminal and a second-inverter output terminal connected to the first data output terminal; c. a third inverter having a third-inverter input terminal connected to the third data terminal and a third-inverter output terminal connected to the second data output terminal; and d. a fourth inverter having a fourth-inverter input terminal connected to the fourth data terminal and a fourth-inverter output terminal connected to the second data output terminal. 9. The data combiner of claim 8, wherein the first-inverter output terminal connects to the data output terminal via a first transistor, the second-inverter output terminal connects to the data output terminal via a second transistor, the third-inverter output terminal connects to the second data output terminal via a third transistor, and the fourth-inverter output terminal connects to the second data output terminal via a fourth transistor. 10. The data combiner of claim 9, wherein the first transistor has a first control terminal connected to the first clock terminal, the second transistor has a second control terminal connected to the second clock terminal, the third transistor has a third control terminal connected to the third clock terminal, and the fourth transistor has a fourth control terminal connected to the fourth clock terminal. 11. The data combiner of claim 8, wherein the third and fourth inverters each comprise complementary transistors. 12. The data combiner of claim 7, wherein the first current source is selectively connected to the first data output terminal via the current-steering circuit, and wherein the second current source is selectively connected to the second data output terminal via the second current-steering circuit. 13. A data combiner comprising: a. a current-steering circuit including: i. a first clock terminal adapted to receive a first clock signal of a first clock phase; ii. a second clock terminal adapted to receive a second clock signal of a second clock phase; iii. a first data terminal adapted to receive a first series of data bits; iv. a second data terminal adapted to receive a second series of data bits synchronized with the first series o