초록 ▼

A hand-held electronic device with a keyboard optimized for use with the thumbs is disclosed. In order to operate within the limited space available on a hand-held electronic device, the present invention optimizes the placement and shape of the keys, preferably using keys that are oval or oblong in

A hand-held electronic device with a keyboard optimized for use with the thumbs is disclosed. In order to operate within the limited space available on a hand-held electronic device, the present invention optimizes the placement and shape of the keys, preferably using keys that are oval or oblong in shape, and that are placed at angles designed to facilitate thumb-typing.

대표청구항 ▼

A hand-held electronic device with a keyboard optimized for use with the thumbs is disclosed. In order to operate within the limited space available on a hand-held electronic device, the present invention optimizes the placement and shape of the keys, preferably using keys that are oval or oblong in

A hand-held electronic device with a keyboard optimized for use with the thumbs is disclosed. In order to operate within the limited space available on a hand-held electronic device, the present invention optimizes the placement and shape of the keys, preferably using keys that are oval or oblong in shape, and that are placed at angles designed to facilitate thumb-typing. 6; US-5731794, 19980300, Miyazawa, 345/088; US-5739809, 19980400, McLaughlin et al., 345/150; US-5886681, 19990300, Walsh et al., 345/102; US-5898414, 19990400, Awamoto et al., 345/055; US-5920358, 19990700, Takemura, 348/655; US-5926239, 19990700, Kumar et al., 349/069; US-5986641, 19991100, Shimamoto, 345/204; US-6023131, 20000200, Okita, 315/291; US-6036327, 20000300, Blonder et al., 362/031; US-6043797, 20000300, Clifton et al., 345/001; US-6072458, 20000600, Asakawa et al., 345/101; US-6184957, 20010200, Mori et al., 349/117; US-6243059, 20010600, Greene et al., 345/001.3; US-6256425, 20010700, Kunzman, 348/742 ally connected to each other, each of said stages comprising: a first transistor having a first control terminal, which is turned on by a signal on a predetermined level supplied from one stage to said first control terminal, and outputs said signal on a predetermined level from one end of a first electric current path to the other end of said first electric current path; a second transistor having a second control terminal, which is turned on in accordance with a voltage applied to a wiring between said second control terminal and the other end of said first electric current path of said first transistor, and outputs a first or second signal supplied from outside to one end of a second electric current path as an output signal from the other end of said second electric current path; a third transistor having a third control terminal, which outputs a power supply voltage from one end of a third electric current path to the other end of said third electric current path; a fourth transistor having a fourth control terminal, which is turned on in accordance with a voltage applied to a wiring between said fourth control terminal and the other end of said first electric current path of said first transistor, and outputs from one end of a fourth electric current path to the other end of said fourth electric current path said power supply voltage supplied from said third transistor so that said power supply voltage outputted from said third transistor is displaced to a voltage on a predetermined level; and a fifth transistor having a fifth control terminal, which is turned on in accordance with a voltage applied to a wiring between said fifth control terminal and said third transistor, has one end of a fifth electric current path being connected to the other end of said second electric current path of said second transistor, and outputs a reference voltage from the other end of said fifth electric current path to one end of said fifth electric current path, a first value indicative of a channel-width/a channel-length of said third transistor being larger than 1/20 of a second value indicative of a channel-width/a channel-length of said second transistor. 4. The shift register according to claim 3, further comprising a sixth transistor having a sixth control terminal, which resets a voltage applied to said wiring between said second control terminal of said second transistor and the other end of said first electric current path of said first transistor by turning on said sixth control terminal by an output signal of the other stage. 5. A shift register comprising a plurality of stages electrically connected to each other, each of said stages comprising: a first transistor having a first control terminal, which is turned on by a signal on a predetermined level supplied from one stage to said first control terminal, and outputs said signal on a predetermined level from one end of a first electric current path to the other end of said first electric current path; a second transistor having a second control terminal, which is turned on in accordance with a voltage applied to a wiring between said second control terminal and the other end of said first electric current path of said first transistor, and outputs a first or second signal supplied from outside to one end of a second electric current path as an output signal from the other end of said second electric current path; a third transistor having a third control terminal, which outputs a power supply voltage from one end of a third electric current path to the other end of said third electric current path; a fourth transistor having a fourth control terminal, which is turned on in accordance with a voltage applied to a wiring between said fourth control terminal and the other end of said first electric current path of said first transistor, and outputs from one end of a fourth electric current path to the other end of said fourth electric current path said power suppl y voltage supplied from said third transistor so that said power supply voltage outputted from said third transistor is displaced to a voltage on a predetermined level; a fifth transistor having a fifth control terminal, which is turned on in accordance with a voltage applied to a wiring between said fifth control terminal and said third transistor, has one end of a fifth electric current path being connected to the other end of said second electric current path of said second transistor, and outputs a reference voltage from the other end of said fifth electric current path to one end of said fifth electric current path; and a sixth transistor having a sixth control terminal, which resets a voltage applied to said wiring between said second control terminal of said second transistor and the other end of said first electric current path of said first transistor by turning on said sixth control terminal by an output signal of the other stage, a first value indicative of a channel-width/a channel-length of said fifth transistor being larger than a second value indicative of a channel-width/a channel-length of said first transistor. 6. The shift register according to claim 5, wherein a third value indicative of a channel-width/a channel-length of said second transistor is larger than said second value. 7. The shift register according to claim 5, wherein said first value is larger than a fourth value indicative of a channel-width/a channel-length of said sixth transistor. 8. The shift register according to claim 5, wherein a third value indicative of a channel-width/a channel-length of said second transistor is larger than a fourth value indicative of a channel-width/a channel-length of said sixth transistor. 9. The shift register according to claim 5, wherein said second value is larger than a fifth value indicative of a channel-width/a channel-length of said third transistor. 10. The shift register according to claim 5, wherein a fourth value indicative of a channel-width/a channel-length of said sixth transistor is larger than a fifth value indicative of a channel-width/a channel-length of said third transistor. 11. The shift register according to claim 5, wherein said second value is larger than a sixth value indicative of a channel-width/a channel-length of said fourth transistor. 12. The shift register according to claim 5, wherein a fourth value indicative of a channel-width/a channel-length of said sixth transistor is larger than a sixth value indicative of a channel-width/a channel-length of said fourth transistor. 13. A shift register comprising a plurality of stages electrically connected to each other, each stage of said shift register comprising: a first transistor having a first control terminal to which an output signal of a stage on one side is supplied and one end of an electric current path to which a first voltage signal is supplied; a second transistor having a second control terminal to which an output signal of a stage on the other side is supplied and one end of an electric current path to which a second voltage signal is supplied; and a third transistor having a third control terminal being connected to the other end of each electric current path of said first and second transistors, which is turned on or off by said first or second voltage signal supplied to a wiring between said third control terminal and said first or second transistor through said first or second transistor, and outputs as an output signal of the corresponding stage from the other end of an electric current path a first or second clock signal supplied to one end of said electric current path when turned on, at least one of said first and second transistors discharging electric charge accumulated in said wiring by an output signal of a stage on one side or the other side supplied to said first or second control terminal. 14. The shift register according to claim 13, wherein one of said first and second transistors of a stage