Lead-free tin silicate-phosphate glass and sealing material containing the same
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
C03C-008/08
C03C-008/14
C03C-003/062
출원번호
US-0863085
(2001-05-22)
발명자
/ 주소
Yamanaka, Toshio
출원인 / 주소
Nippon Electric Glass Co. Ltd.
대리인 / 주소
Collard & Roe, P.C.
인용정보
피인용 횟수 :
4인용 특허 :
4
초록▼
A sealing material for electric parts containing a lead-free tin silicate-phosphate glass of 50-100 volume percents and refractory fillers of the balance. The lead free tin silicate-phosphate glass consists essentially of, by molecular percent, 30-80% SnO, 5.5-20% SiO2,and 10-50% P2O5. The glass may
A sealing material for electric parts containing a lead-free tin silicate-phosphate glass of 50-100 volume percents and refractory fillers of the balance. The lead free tin silicate-phosphate glass consists essentially of, by molecular percent, 30-80% SnO, 5.5-20% SiO2,and 10-50% P2O5. The glass may contain at least one of glass stabilizing elements, said glass stabilizing elements including 3-25% ZnO, 0-4.9% B2O3,0-5% Al2O3,0-10% WO3,0-10% MoO3,0-10% Nb2O5,0-10% TiO2,0-10% ZrO2,0-15% R2O (R is Li, Na, K, and/or Cs), 0-5% CuO, 0-5% MnO, 0-10% R'O (R' is Mg, Ca, Sr and/or Ba), a total content of at least one of the glass stabilizing elements being up to 40%.
대표청구항▼
A sealing material for electric parts containing a lead-free tin silicate-phosphate glass of 50-100 volume percents and refractory fillers of the balance. The lead free tin silicate-phosphate glass consists essentially of, by molecular percent, 30-80% SnO, 5.5-20% SiO2,and 10-50% P2O5. The glass may
A sealing material for electric parts containing a lead-free tin silicate-phosphate glass of 50-100 volume percents and refractory fillers of the balance. The lead free tin silicate-phosphate glass consists essentially of, by molecular percent, 30-80% SnO, 5.5-20% SiO2,and 10-50% P2O5. The glass may contain at least one of glass stabilizing elements, said glass stabilizing elements including 3-25% ZnO, 0-4.9% B2O3,0-5% Al2O3,0-10% WO3,0-10% MoO3,0-10% Nb2O5,0-10% TiO2,0-10% ZrO2,0-15% R2O (R is Li, Na, K, and/or Cs), 0-5% CuO, 0-5% MnO, 0-10% R'O (R' is Mg, Ca, Sr and/or Ba), a total content of at least one of the glass stabilizing elements being up to 40%. thereabove. 5. The method of claim 1, wherein performing a wet etching process comprises performing a wet etching process in a dilute hydrofluoric acid bath. 6. The method of claim 1, wherein performing a wet etching process comprised of a duration parameter on said process layer to reduce a thickness of said process layer comprises performing a wet etching process comprised of a duration parameter on said process layer to reduce a thickness of said process layer to a thickness of approximately 2-6 nm. 7. The method of claim 1, wherein adjusting said duration parameter of said wet etching process if said reduced thickness of said process layer after said etching process is complete is not within acceptable limits comprises adjusting said duration parameter of said wet etching process if said reduced thickness of said process layer after said etching process is complete is not within a preselected range. 8. The method of claim 1, further comprising measuring said reduced thickness of said process layer after said etching process is performed and providing said measured thickness to a controller. 9. A method, comprising: providing a substrate comprised of silicon having a process layer comprised of at least one of silicon dioxide, silicon nitride, silicon oxynitride, and a material having a dielectric constant less than 5.0 formed thereabove; performing a wet etching process comprised of a duration parameter on said process layer to reduce a thickness of said process layer to thereby form a gate insulation layer for an integrated circuit device; adjusting said duration parameter of said wet etching process if said reduced thickness of said process layer after said etching process is complete is not within a preselected range; and performing said wet etching process comprised of said adjusted duration parameter on a process layer formed on at least one subsequently processed substrate to thereby form a gate insulation layer for an integrated circuit device formed on said subsequently processed substrate. 10. The method of claim 9, wherein providing a substrate having a process layer formed thereabove comprises providing a substrate having a process layer formed thereabove by a deposition process. 11. The method of claim 9, wherein performing a wet etching process comprises performing a wet etching process in a dilute hydrofluoric acid bath. 12. The method of claim 9, wherein performing a wet etching process comprised of a duration parameter on said process layer to reduce a thickness of said process layer comprises performing a wet etching process comprised of a duration parameter on said process layer to reduce a thickness of said process layer to a thickness of approximately 2-6 nm. 13. The method of claim 9, further comprising measuring said reduced thickness of said process layer after said etching process is performed and providing said measured thickness to a controller. 14. A method, comprising: providing a substrate; thermally growing a process layer comprised of silicon dioxide above said substrate; performing a wet etching process comprised of a duration parameter on said process layer to reduce a thickness of said process layer to thereby form a gate insulation layer for an integrated circuit device, said wet etching process being performed in an etch bath comprised of hydrofluoric acid; adjusting said duration parameter of said wet etching process if said reduced thickness of said process layer after said etching process is complete is not within acceptable limits; and performing said wet etching process comprised of said adjusted duration parameter on a process layer formed on at least one subsequently processed substrate to thereby form a gate insulation layer for an integrated circuit device formed on said subsequently processed substrate. 15. The method of claim 14, wherein providing a substrate comprises providing a substrate comprised of silicon. 16. The method of claim 14, wherein performing a
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이 특허에 인용된 특허 (4)
Hiroshi Usui JP; Yasuko Dotani JP; Ryuichi Tanabe JP; Tsuneo Manabe JP, Low melting point glass and glass ceramic composition.
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