[미국특허]
Low power tunneling metal-oxide-semiconductor (MOS) device
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-029/76
H01L-029/94
H01L-031/062
H01L-031/113
H01L-031/119
출원번호
US-0185338
(2002-06-28)
발명자
/ 주소
Goodwin-Johansson, Scott H.
출원인 / 주소
MCNC
대리인 / 주소
Alston & Bird LLP
인용정보
피인용 횟수 :
90인용 특허 :
17
초록▼
A three terminal tunneling device that has a smaller voltage transition between off-current and on-current states and which also has less dependence on the lateral dimensions of the device. The device is a hybrid between a MOS transistor, a gated diode and a tunneling diode. The semiconductor device
A three terminal tunneling device that has a smaller voltage transition between off-current and on-current states and which also has less dependence on the lateral dimensions of the device. The device is a hybrid between a MOS transistor, a gated diode and a tunneling diode. The semiconductor device includes a lightly doped substrate of a first conductivity type. The lightly doped substrate will include a first heavily doped region of a first conductivity type formed in the substrate and a lightly doped layer of a first conductivity type disposed on the substrate and the first heavily doped region. The device also including a gate insulator layer disposed on the lightly doped layer and underlying a portion of the first heavily doped region and a gate electrode that is disposed on the gate insulator layer. Additionally, the device will include a second heavily doped region of a first conductivity formed in the substrate extending into the first heavily doped region of a first conductivity and a heavily doped region of a second conductivity formed in the substrate extending into the lightly doped substrate and spatially isolated from the first heavily doped region.
대표청구항▼
A three terminal tunneling device that has a smaller voltage transition between off-current and on-current states and which also has less dependence on the lateral dimensions of the device. The device is a hybrid between a MOS transistor, a gated diode and a tunneling diode. The semiconductor device
A three terminal tunneling device that has a smaller voltage transition between off-current and on-current states and which also has less dependence on the lateral dimensions of the device. The device is a hybrid between a MOS transistor, a gated diode and a tunneling diode. The semiconductor device includes a lightly doped substrate of a first conductivity type. The lightly doped substrate will include a first heavily doped region of a first conductivity type formed in the substrate and a lightly doped layer of a first conductivity type disposed on the substrate and the first heavily doped region. The device also including a gate insulator layer disposed on the lightly doped layer and underlying a portion of the first heavily doped region and a gate electrode that is disposed on the gate insulator layer. Additionally, the device will include a second heavily doped region of a first conductivity formed in the substrate extending into the first heavily doped region of a first conductivity and a heavily doped region of a second conductivity formed in the substrate extending into the lightly doped substrate and spatially isolated from the first heavily doped region. ductor region which is adjacent to the source region and formed by introducing an impurity of the first conductivity type in the direction of the channel region placed under the floating gate electrode from an end on the source side, of the floating gate electrode, and which has an impurity concentration relatively higher than that of the channel region. 6. The semiconductor device according to claim 1, wherein the source and drain regions comprise a low-concentration semiconductor region of relatively low impurity concentration and a high-concentration semiconductor region of relatively high impurity concentration, and the first semiconductor region, the low-concentration semiconductor region, and the high-concentration semiconductor region are formed in order from the side that faces the channel region. 7. A semiconductor device comprising: a plurality of nonvolatile memory cells arranged on a semiconductor substrate in matrix form, each including, a gate insulating film covering a channel region in a main surface of the semiconductor substrate of a first conductivity type, a floating gate electrode, an interlayer film and a control gate electrode successively formed; source and drain regions of a second conductivity type formed in the semiconductor substrate on both sides opposite to each other, of the floating gate electrode so as to interpose a channel region located under the floating gate electrode therebetween; a first semiconductor region which is adjacent to the drain region and formed by introducing an impurity of a second conductivity type in the direction of the channel region placed under the floating gate electrode from an end on the drain side, of the floating gate electrode, and which has an impurity concentration relatively lower than that of the drain region; and a second semiconductor region which is adjacent to the first semiconductor region and formed by introducing an impurity of the first conductivity type in the direction of the channel region placed under the floating gate electrode from an end on the drain side, of the floating gate electrode, and which has an impurity concentration relatively higher than that of the channel region, wherein the source and drain regions of the plurality of nonvolatile memory cells are parallel-connected to one another in respective columns, wherein word lines which constitute the control gate electrodes of the plurality of nonvolatile memory cells, extend in respective rows, wherein a voltage is applied to at least one word line, which is set so as to serve as a selected word line, and wherein when carriers are stored in a floating gate electrode of a nonvolatile memory cell connected to the selected word line, a negative voltage is applied to other non-selected word lines other than the selected word line. 8. The semiconductor device according to claim 7, wherein the impurity of the second conductivity type, which constitutes the first semiconductor region, is phosphorus. 9. The semiconductor device according to claim 7, wherein the storage of the carriers in the floating gate electrode of the nonvolatile memory cell is carried out by hot-electron injection of electrons having obtained high energy in the neighborhood of the end of the drain region into the floating gate electrode. 10. The semiconductor device according to claim 7, wherein the discharge of carriers from the floating gate electrode of the nonvolatile memory cell is carried out by tunnel emission of the electrons in the floating gate electrode into the semiconductor substrate. 11. The semiconductor device according to claim 7, further including a third semiconductor region which is adjacent to the source region and formed by introducing an impurity of the first conductivity type in the direction of the channel region placed under the floating gate electrode from an end on the source side, of the floating gate electrode, and which has an impurity concentration relatively higher than that o f the channel region. 12. The semiconductor device according to claim 7, wherein the source and drain regions comprise a low-concentration semiconductor region of relatively low impurity concentration and a high-concentration semiconductor region of relatively high impurity concentration, and the first semiconductor region, the low-concentration semiconductor region, and the high-concentration semiconductor region are formed in order from the side that faces the channel region. 13. A semiconductor device comprising: a plurality of nonvolatile memory cells arranged on a semiconductor substrate in matrix form, each including a gate insulating film covering a channel region in a main surface of the semiconductor substrate of a first conductivity type, a floating gate electrode, an interlayer film and a control gate electrode successively formed; source and drain regions of a second conductivity type formed in the semiconductor substrate on both sides opposite to each other, of the floating gate electrode so as to interpose a channel region located under the floating gate electrode therebetween; a first semiconductor region which is adjacent to the drain region and formed by introducing an impurity of the second conductivity type in the direction of the channel region placed under the floating gate electrode from an end on the drain side, of the floating gate electrode, and which has an impurity concentration relatively lower than that of the drain region; and a second semiconductor region which is adjacent to the first semiconductor region and formed by introducing an impurity of the first conductivity type in the direction of the channel region placed under the floating gate electrode from an end on the drain side, of the floating gate electrode, and which has an impurity concentration relatively higher than that of the channel region, wherein the control gate electrode is electrically connected to a corresponding word line, and a negative voltage is applied to each non-selected word line upon a write operation, wherein storage of the carriers in the floating gate electrode of the nonvolatile memory cell is carried out by hot-electron injection of electrons having obtained high energy in the neighborhood of the end of the drain region into the floating gate electrode, and wherein the source and drain regions comprise a low-concentration semiconductor region of relatively low impurity concentration and a high-concentration semiconductor region of relatively high impurity concentration, and the first semiconductor region, the low-concentration semiconductor region, and the high-concentration semiconductor region are formed in order from the side that faces the channel region. 14. The semiconductor device according to claim 13, wherein the impurity of the second conductivity type, which constitutes the first semiconductor region, is phosphorus.
Chin-Yu Tsai TW; Taylor R. Efland ; Sameer Pendharkar ; John P. Erdeljac ; Jozef Mitros ; Jeffrey P. Smith ; Louis N. Hutter, LDMOS power device with oversized dwell.
Cavanaugh Marion E. (792 Paul Ave. Palo Alto CA 94306), Quantum field effect device with source extension region formed under a gate and between the source and drain regions.
Russell Lewis K. (San Jose CA) Dao Tich T. (Cupertino CA) Muller Richard S. (Kensington CA), Threshold switching integrated circuit and method for forming the same.
Cheng, Zhiyuan; Fiorenza, James; Hydrick, Jennifer M.; Lochtefeld, Anthony J.; Park, Ji-Soo; Bai, Jie; Li, Jizhong, Formation of devices by epitaxial layer overgrowth.
Hydrick, Jennifer M.; Li, Jizhong; Cheng, Zhinyuan; Fiorenza, James; Bai, Jie; Park, Ji-Soo; Lochtefeld, Anthony J., Formation of devices by epitaxial layer overgrowth.
Li, Jizhong; Lochtefeld, Anthony J., Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication.
Lochtefeld, Anthony J.; Currie, Matthew T.; Cheng, Zhiyuan; Fiorenza, James; Braithwaite, Glyn; Langdo, Thomas A., Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication.
Lochtefeld, Anthony J.; Currie, Matthew T.; Cheng, Zhiyuan; Fiorenza, James; Braithwaite, Glyn; Langdo, Thomas A., Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication.
Lochtefeld, Anthony J.; Currie, Matthew T.; Cheng, Zhiyuan; Fiorenza, James; Braithwaite, Glyn; Langdo, Thomas A., Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication.
Lochtefeld, Anthony J.; Currie, Matthew T.; Cheng, Zhiyuan; Fiorenza, James; Braithwaite, Glyn; Langdo, Thomas A., Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication.
Lochtefeld, Anthony J.; Currie, Matthew T.; Cheng, Zhiyuan; Fiorenza, James; Braithwaite, Glyn; Langdo, Thomas A., Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication.
Lochtefeld, Anthony J.; Currie, Matthew T.; Cheng, Zhiyuan; Fiorenza, James; Braithwaite, Glyn; Langdo, Thomas A., Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication.
Lochtefeld, Anthony J.; Currie, Matthew T.; Cheng, Zhiyuan; Fiorenza, James; Braithwaite, Glyn; Langdo, Thomas A., Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication.
Przybysz, John Xavier; Baumgardner, James E.; Pesetski, Aaron A.; Miller, Donald Lynn; Herr, Ouentin P., Method and apparatus for controlling qubits with single flux quantum logic.
Przybysz, John Xavier; Baumgardner, James E.; Pesetski, Aaron A.; Miller, Donald Lynn; Herr, Quentin P., Method and apparatus for controlling qubits with single flux quantum logic.
Lochtefeld, Anthony J.; Currie, Matthew T.; Cheng, Zhi Yuan; Fiorenza, James, Solutions for integrated circuit integration of alternative active area materials.
Hou, Yung-Chin; Lu, Lee-Chung; Guo, Ta-Pen; Tien, Li-Chun; Li, Ping Chung; Tai, Chun-Hui; Chen, Shu-Min, Standard cell without OD space effect in Y-direction.
Ko, Chih-Hsin; Lee, Wen-Chin; Yeo, Yee-Chia; Lin, Chun-Chieh; Hu, Chenming, Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit.
Ko,Chih Hsin; Lee,Wen Chin; Yeo,Yee Chia; Lin,Chun Chieh; Hu,Chenming, Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.