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Interposer and method of making same 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/522
  • H01L-023/485
  • H01L-023/488
출원번호 US-0340530 (1999-06-28)
발명자 / 주소
  • Bohr, Mark T.
출원인 / 주소
  • Intel Corporation
대리인 / 주소
    Blakely, Sokoloff, Taylor & Zafman LLP
인용정보 피인용 횟수 : 61  인용 특허 : 27

초록

A structure suitable for connecting an integrated circuit to a supporting substrate wherein the structure has thermal expansion characteristics well-matched to the integrated circuit is an interposer. The integrated circuit and the interposer are comprised of bodies that have substantially similar c

대표청구항

1. An electronic assembly comprising: a die including a silicon substrate, the die comprising a first plurality of insulated gate field effect transistors having a first set of electrical characteristics; an interposer including a first surface and an opposing second surface, the first surface a

이 특허에 인용된 특허 (27)

  1. Anthony Thomas R. (Schenectady NY), Alignment-enhancing feed-through conductors for stackable silicon-on-sapphire wafers.
  2. Nakajima Yasushi,JPX, Assembly of semiconductor device.
  3. Ahmad Umar M. ; Atwood Eugene R., Bare die multiple dies for direct attach.
  4. Lin Paul T. (Austin TX), Composite flip chip semiconductor device with an interposer having test contacts formed along its periphery.
  5. Sato Noriaki,JPX, ESD tolerated SOI device.
  6. Honn ; James J. ; Stuby ; Kenneth P., Electrical package for LSI devices and assembly process therefor.
  7. Paniccia Mario ; Burton Edward, Flip-chip having an on-chip cache memory.
  8. Wu Andrew L. (Shrewsbury) Smelser Donald W. (Bolton) Bruce ; II E. William (Lunenburg MA) O\Dea John (Galway IRX), High density memory array packaging.
  9. Jacobs Scott L. (Chester VA) Nihal Perwaiz (Hopewell Junction NY) Ozmat Burhan (Peekskill NY) Schnurmann Henri D. (Monsey NY), High performance integrated circuit packaging structure.
  10. Baldwin ; Steven M. ; Henderson ; Sr. ; Donald L. ; Karp ; Joel A., IGFET Integrated circuit memory cell.
  11. Weiler Peter M. (Alpine UT) Belani Jagdish G. (Cupertino CA), Integrated circuit package assemblies including an electrostatic discharge interposer.
  12. Switky Andrew (Palo Alto CA), Integrated socket and IC package assembly.
  13. Inasaka Jun (Tokyo JPX), Laminate wiring board.
  14. Kresge John S. (Binghamton NY) Light David N. (Friendsville PA) Wu Tien Y. (Endwell NY), Laminated electronic package including a power/ground assembly.
  15. Rostoker Michael D. (Boulder Creek CA) Kapoor Ashok K. (Palo Alto CA), Metal interconnect structures for use with integrated circuit devices to form integrated circuit structures.
  16. Beilstein ; Jr. Kenneth Edward ; Bertin Claude Louis ; Cronin John Edward ; Howell Wayne John ; Leas James Marc ; Perlman David Jacob, Method and workpiece for connecting a thin layer to a monolithic electronic module's surface and associated module pac.
  17. Hoenlein Wolfgang (Unterhaching DEX) Schwarzl Siegfried (Neubiberg DEX), Method for manufacturing a cubically integrated circuit arrangement.
  18. Geller Bernard D. (Rockville MD) Tyler Johann U. (Mt. Airy MD) Holdeman Louis B. (Boyds MD) Phelleps Fred R. (Gaithersburg MD) Laird ; III George F. (Baltimore MD), Method of packaging microwave semiconductor components and integrated circuits.
  19. Jacobs Scott L. (Peekskill NY) Nihal Perwaiz (Hopewell Junction NY) Ozmat Burhan (Peekskill NY) Schnurmann Henri D. (Monsey NY) Zingher Arthur R. (White Plains NY), Module for packaging semiconductor integrated circuit chips on a base substrate.
  20. Ito Jun-ichi (Tokuyama JPX) Shimamoto Toshitsugu (Fujisawa JPX), Multilayer board and fabrication method thereof.
  21. Miyake Michael K. (Westminster CA), Non-conductive end layer for integrated stack of IC chips.
  22. Stager Mark P. ; Yee Abraham F. ; Padmanabhan Gobi R., Semiconductor chip package with interconnect layers and routing and testing methods.
  23. Wenzel James F. (Austin TX) Chopra Mona A. (Austin TX) Foster Stephen W. (Dripping Springs TX), Semiconductor device having built-in high frequency bypass capacitor.
  24. Fujita Yuuji (Koganei JPX) Mizuishi Kenichi (Hachioji JPX), Semiconductor substrate having wiring conductors at a first main surface electrically connected to plural pins at a seco.
  25. Liberkowski Janusz B. (5884 Macadam Ct. San Jose CA 95123), Signal-routing or interconnect substrate, structure and apparatus.
  26. Palmer David W. ; Gassman Richard A. ; Chu Dahwey, Silicon ball grid array chip carrier.
  27. Tazunoki Masanori (Nishitama) Mishimagi Hiromitsu (Akishima) Homma Makoto (Nishitama) Sakuta Toshiyuki (Nishitama) Nakamura Hisashi (Ohme) Sasaki Keiji (Musashino) Enomoto Minoru (Tokorozawa) Satoh T, Wafer scale of full wafer memory system, packaging method thereof, and wafer processing method employed therein.

이 특허를 인용한 특허 (61)

  1. Cooney, Robert C.; Wilkinson, Joseph M., Circuit board with an attached die and intermediate interposer.
  2. Ho,Kwun Yao; Kung,Moriss, Electrical package capable of increasing the density of bonding pads and fine circuit lines inside a interconnection.
  3. Roozeboom, Freddy; Buijsman, Adrianus Alphonsus Jozef; Gamand, Patrice; Kemmeren, Antonius Lucien Adrianus Maria; Hubert, Gerardus Tarcisius Maria, Electronic device, assembly and methods of manufacturing an electronic device including a vertical trench capacitor and a vertical interconnect.
  4. Palanduz, Cengiz A., High-k thin film grain size control.
  5. Chainer, Timothy J., Integrated chip carrier with compliant interconnects.
  6. Monchiero, Matteo; Leverich, Jacob B.; Ranganathan, Parthasarathy; Jouppi, Norman Paul; Talwar, Vanish, Integrated circuit package.
  7. Choi, A Leam; Chung, Jae Han; Yang, DeokKyung; Park, HyungSang, Integrated circuit packaging system having through silicon via with direct interconnects and method of manufacture thereof.
  8. Choi, A Leam; Chung, Jae Han; Yang, DeokKyung; Park, HyungSang, Integrated circuit packaging system having through silicon via with direct interconnects and method of manufacture thereof.
  9. Huang, Rui; Bao, Xusheng; Chen, Kang; Hsiao, Yung Kuan; Goh, Hin Hwa, Integrated circuit packaging system with a substrate embedded dummy-die paddle and method of manufacture thereof.
  10. Ramachandran, Vidhya; Ray, Urmi; Shenoy, Ravindra Vaman; Lai, Kwan-Yu; Lasiter, Jon Bradley, Integrated interposer with embedded active devices.
  11. Babakhani, Aydin; Cordes, Steven A.; Plouchart, Jean-Olivier; Reynolds, Scott K.; Sorce, Peter J.; Trzcinski, Robert E., Integration of photonic, electronic, and sensor devices with SOI VLSI microprocessor technology.
  12. Babakhani, Aydin; Cordes, Steven A.; Plouchart, Jean-Olivier; Reynolds, Scott K.; Sorce, Peter J.; Trzcinski, Robert E., Integration of photonic, electronic, and sensor devices with SOI VLSI microprocessor technology.
  13. Babakhani, Aydin; Cordes, Steven A.; Plouchart, Jean-Olivier; Reynolds, Scott K.; Sorce, Peter J.; Trzcinski, Robert E., Integration of photonic, electronic, and sensor devices with SOI VLSI microprocessor technology.
  14. White, George E.; Dalmia, Sidharth, Integration using package stacking with multi-layer organic substrates.
  15. Bohr,Mark T., Interposer and method of making same.
  16. Conn, Robert O., Interposer for redistributing signals.
  17. Conn, Robert O., Interposing structure.
  18. Kuo, Chien-Li; Lin, Yung-Chang, Method for forming semiconductor device with through silicon via.
  19. Cooney, Robert C.; Wilkinson, Joseph M., Method of attaching die to circuit board with an intermediate interposer.
  20. Iadanza, Joseph A., Method of connecting core I/O pins to backside chip I/O pads.
  21. Gautham,Viswanadam; Tan,Lan Chu, Method of making reinforced semiconductor package.
  22. Omote, Koji; Mizukoshi, Masataka; Taniguchi, Osamu, Method of manufacturing electronic circuit component.
  23. Palanduz, Cengiz A., Methods of making thin film capacitors.
  24. Palanduz, Cengiz A.; Min, Yongki, Passive device structure.
  25. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  26. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  27. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  28. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  29. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  30. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  31. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chip.
  32. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chips.
  33. Mune, Kazunori; Fujii, Hirofumi; Tanigawa, Satoshi, Process for manufacturing a printed wiring board.
  34. Hsu, Chao-Shun; Chao, Clinton; Peng, Mark Shane, Programmable semiconductor interposer for electronic package and method of forming.
  35. Hsu, Chao-Shun; Chao, Clinton; Peng, Mark Shane, Programmable semiconductor interposer for electronic package and method of forming.
  36. Satoh, Toshiya; Ogino, Masahiko; Miwa, Takao; Naitou, Takashi; Namekawa, Takashi, Semiconductor connection substrate.
  37. Kawano, Masaya, Semiconductor device.
  38. Kuo, Chien-Li; Lin, Yung-Chang, Semiconductor device.
  39. Yamagata, Osamu, Semiconductor device.
  40. Kanamori, Hiroshi; Otsuka, Shigeki; Morita, Yuichi; Suzuki, Akira, Semiconductor device and manufacturing method of the same.
  41. Hayashi, Kenta; Yamamoto, Katsumi; Nakamura, Makoto; Akiyama, Naoyuki; Taguchi, Kyosuke, Semiconductor device and method for manufacturing same.
  42. Kawano, Masaya, Semiconductor device and method for manufacturing the same.
  43. Kawano, Masaya, Semiconductor device and method for manufacturing the same.
  44. Yamagata,Osamu, Semiconductor device and method of fabricating the same.
  45. Tago, Masamoto, Semiconductor device and wiring board.
  46. Kawano, Masaya, Semiconductor device comprising through-electrode interconnect.
  47. Kawano, Masaya, Semiconductor device comprising through-electrode interconnect.
  48. Otremba, Ralf, Semiconductor module with a power semiconductor chip and a passive component and method for producing the same.
  49. Otremba, Ralf, Semiconductor module with a semiconductor chip and a passive component and method for producing the same.
  50. Briere, Michael A., Semiconductor package with integrated passives and method for fabricating same.
  51. Magerlein, John H.; Patel, Chirag S.; Sprogis, Edmund J.; Stoller, Herbert I., Silicon based package.
  52. Chen, Chih-Hua, Test patterns for detecting misalignment of through-wafer vias.
  53. Palanduz, Cengiz A., Thin film capacitors and methods of making the same.
  54. Palanduz,Cengiz A., Thin film capacitors and methods of making the same.
  55. Yakabe, Masami; Kagawa, Kenichi; Hoshino, Tomohisa, Through substrate, interposer and manufacturing method of through substrate.
  56. Berg, John E.; Hackler, Sr., Douglas R., Triple-damascene interposer.
  57. Arai, Tadashi, Wiring board, manufacturing method of the wiring board, and semiconductor package.
  58. Chinda,Akira; Matsuura,Akira; Yoshiwa,Takayuki; Mita,Mamoru; Kageyama,Takashi; Taga,Katsutoshi, Wiring board, method for manufacturing wiring board and electronic component using wiring board.
  59. Sunohara, Masahiro, Wiring substrate.
  60. Palanduz, Cengiz A.; Wood, Dustin P., iTFC with optimized C(T).
  61. Palanduz, Cengiz A.; Wood, Dustin P., iTFC with optimized C(T).
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