IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0081131
(2002-02-22)
|
우선권정보 |
GB-20010007023 (2001-03-21); GB-20010004565 (2001-02-23) |
발명자
/ 주소 |
- Langford, David John
- Harvey, John Herbert
- Jones, Tony
- Somerfield, Michael Paul
- Brown, Melanie Zoe
|
출원인 / 주소 |
|
대리인 / 주소 |
Andrus, Sceales, Starke & Sawall
|
인용정보 |
피인용 횟수 :
3 인용 특허 :
3 |
초록
▼
A thrust reverser actuator lock mechanism comprising a rotatable shaft, rotation of which in one direction from a rest position drives an associated thrust reverser from a stowed position towards an operative position in use, retractable abutment means having a rest position abutting an element rota
A thrust reverser actuator lock mechanism comprising a rotatable shaft, rotation of which in one direction from a rest position drives an associated thrust reverser from a stowed position towards an operative position in use, retractable abutment means having a rest position abutting an element rotatable with the shaft to prevent rotation of the shaft, resilient means urging said abutment means to said rest position, and, mechanical latch means sensitive to the speed of rotation of said shaft for latching said abutment means in a retracted position against the action of said resilient means when the rotational speed of said shaft exceeds a predetermined value.
대표청구항
▼
A thrust reverser actuator lock mechanism comprising a rotatable shaft, rotation of which in one direction from a rest position drives an associated thrust reverser from a stowed position towards an operative position in use, retractable abutment means having a rest position abutting an element rota
A thrust reverser actuator lock mechanism comprising a rotatable shaft, rotation of which in one direction from a rest position drives an associated thrust reverser from a stowed position towards an operative position in use, retractable abutment means having a rest position abutting an element rotatable with the shaft to prevent rotation of the shaft, resilient means urging said abutment means to said rest position, and, mechanical latch means sensitive to the speed of rotation of said shaft for latching said abutment means in a retracted position against the action of said resilient means when the rotational speed of said shaft exceeds a predetermined value. sis and optimazation", Oct. 1992. IEEE, pp. 328-333. Pfleeger, "state reduction of completely specified FSM's", 1973. IEEE, pp. 1099-1102. Demir, Alper, et al., "Modeling and Simulation of the Interference due to Digital Switching in Mixed-Signal ICs," 1999 IEEE/ACM International Conference on Computer-Aided Design, Nov. 7-11, 1999, pp. 70-74. Charbon, E., "Hierarchical Watermarking in IC Design," Proc. IEEE Custom Integrated Circuits Conference, May 1998, pp. 295-298. Charbon, E., et al., "Watermarking Layout Topologies," IEEE Asia-South Pacific Design Automation Conference, May 1999, pp. 213-216. Torunoglu, I., et al, "Watermarking-Based Copyright Protection of Sequential Functions." Swanson, et al., "Transparent Robust Image Watermarking", in Proc, IEEE International Conference in Image Processing, vol. 3, pp. 211-214, Sep. 1996. Boney, et al., "Digital Watermarks for Audio Signals", in Proc. IEEE International Conference on Multimedia Computing and Systems, pp. 473-480, Jun. 1996. Lach, et al., "FPGA Fingerprinting Techniques for Protecting Intellectual Property". In Proc. IEEE Custom Integrated Circuit Conference, pp. 299-302, May 1998. Kahng, et al., "Robust IP Watermarking Methodologies for Physical Design" in Proc. IEEE/ACM Design Automation Conference. pp. 782-787, Jun. 1998. Villa, et al., "Synthesis of Finite State Machines: Logic Optimization, " Chapter 5 -Symbolic Minimization; Kluwer Academic Publ., Boston, MA 1997. De. Micheli, "Synthesis and Optimization of Digital Circuits". Chapter 9 -Sequential Logic Optimization-McGraw-Hill, 1994. inspecting the bits set in said code usage register. 7. The method of claim 5, further comprising the step of: determining which of the plurality of registers is used in each one of the plurality of blocks of code in the computer program. 8. The method of claim 7, further comprising the step of: setting each one of said plurality of storage bits in one of a plurality of storage code usage registers for each register used in each one of the plurality of blocks of code in the computer program. 9. A register usage indicator system for efficiently signaling register usage in a computer program comprising a plurality of blocks of code, said register usage indicator system comprising: means for determining which of a plurality of registers are used in one of the plurality of blocks of code in the computer program; means for setting one of a plurality of storage bits in a code usage register for each one of the plurality of registers used in one of the plurality of blocks of code in the computer program; and means for determining which of said registers are not used in any of the plurality of blocks of code in the computer program by performing a logical OR of all of said plurality of storage bits in the code usage register. 10. The apparatus of claim 9, further comprising: means for inspecting the bits set in said code usage register to determine which of said registers are used in one of the plurality of blocks of code in the computer program. 11. The apparatus of claim 10, further comprising: means for setting each one of said plurality of storage bits in one of a plurality of storage code usage registers for each register used in each one of the plurality of blocks of code in the computer program. 12. The apparatus of claim 9, further comprising: means for determining which of the plurality of registers is used in each one of the plurality of blocks of code in the computer program. 13. A computer-readable medium storing a computer program for efficiently obtaining and utilizing register usage information during software binary translation, comprising: logic configured to determine which of a plurality of registers are used in one of a plurality of blocks of code in the computer program; logic configured to set one of a plurality of storage bits in a code usage register for each one of the plurality of registers used in one of the plurality of blocks of code in the computer program; and logic configured to determine which of the plurality of registers are not used in all of a plurality of blocks of code by performing a logical OR of all of said plurality of storage bits in the code usage register. 14. The computer-readable medium of claim 13, further comprising: logic configured to determine which of said registers are used in one of the plurality of blocks of code in the computer program by inspecting the bits set in said code usage register. 15. The computer-readable medium of claim 13, further comprising: logic configured to determine which of the plurality of registers is used in each one of the plurality of blocks of code in the computer program. 16. The computer-readable medium of claim 15, further comprising: logic configured to set each one of said plurality of storage bits in one of a plurality of storage code usage registers for each register used in each one of the plurality of blocks of code in the computer program.
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