IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0969252
(2001-10-02)
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발명자
/ 주소 |
- Ritz, Charles Louis
- Margolin, George David
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출원인 / 주소 |
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인용정보 |
피인용 횟수 :
10 인용 특허 :
3 |
초록
▼
A heat removal system for integrated circuit chips, lasers, portable electronic devices, and the like which produce destructive amounts of heat employs a device which delivers working fluid to a high heat flux surface in a manner to avoid any change in phase of the fluid. The invention is based on t
A heat removal system for integrated circuit chips, lasers, portable electronic devices, and the like which produce destructive amounts of heat employs a device which delivers working fluid to a high heat flux surface in a manner to avoid any change in phase of the fluid. The invention is based on the recognition that the heat flux produced by such sources is so high that prior art heat sinks fail to remove heat at a sufficient rate from a high heat flux surface and become inefficient in removing heat. The fluid here is maintained at a pressure and pumped at a rate to provide a sufficiently short dwell time to maintain the fluid in a supracritical state thus avoiding vapor lock. The fluid also may be cooled by, for example, either an evaporative or an absorption chiller driven by the heat from the heat source or by a thermoelectric cooler.
대표청구항
▼
A heat removal system for integrated circuit chips, lasers, portable electronic devices, and the like which produce destructive amounts of heat employs a device which delivers working fluid to a high heat flux surface in a manner to avoid any change in phase of the fluid. The invention is based on t
A heat removal system for integrated circuit chips, lasers, portable electronic devices, and the like which produce destructive amounts of heat employs a device which delivers working fluid to a high heat flux surface in a manner to avoid any change in phase of the fluid. The invention is based on the recognition that the heat flux produced by such sources is so high that prior art heat sinks fail to remove heat at a sufficient rate from a high heat flux surface and become inefficient in removing heat. The fluid here is maintained at a pressure and pumped at a rate to provide a sufficiently short dwell time to maintain the fluid in a supracritical state thus avoiding vapor lock. The fluid also may be cooled by, for example, either an evaporative or an absorption chiller driven by the heat from the heat source or by a thermoelectric cooler. stantially similar stacked modules. 11. The stacked semiconductor device assembly of claim 1, wherein each of said semiconductor devices is positioned in a recess of one of said stacked substrates. 12. The stacked semiconductor device assembly of claim 1, further comprising a termination substrate comprising a ground plane and a terminal resistor. 13. The stacked semiconductor device assembly of claim 12, wherein said termination substrate further comprises a power plane decoupled from said ground plane by a capacitor. 14. The stacked semiconductor device assembly of claim 1, further comprising a heat spreader disposed between adjacent stacked substrates. 15. The stacked semiconductor device assembly of claim 14, wherein said heat spreader further comprises a cooling fin. 16. The stacked semiconductor device assembly of claim 1, further comprising a channel for cooling fluid. 17. The stacked semiconductor device assembly of claim 1, wherein said plurality of stacked substrates are adhered to one another with an adhesive. 18. The stacked semiconductor device assembly of claim 1, wherein said plurality of stacked substrates are held together by at least one mechanical fastener. 19. The stacked semiconductor device assembly of claim 1, further comprising a plurality of electrical traces interconnecting ones of said first plurality of terminals and ones of said second plurality of terminals. 20. The stacked semiconductor device assembly of claim 1, wherein each said stacked substrate is configured to receive at least two of said semiconductor devices, wherein said first plurality of terminals of each of said stacked substrates is configured to receive ones of the elongate contact elements of said at least two semiconductor devices. 21. A stacking substrate for use in a stacked semiconductor device assembly, comprising: a substrate having a plurality of faces, said plurality of faces comprising a first face and a second face spaced apart from said first face and configured to mount thereto, and a third face configured for mounting to a semiconductor device; a first plurality of contact elements disposed adjacent to said first face; a second plurality of contact elements disposed adjacent to said second face; a third plurality of contact elements disposed adjacent to said third face; and a plurality of conductive traces interior to said substrate, ones of which are connected to corresponding ones of said first plurality of contact elements, corresponding ones of said second plurality of contact elements, and corresponding ones of said third plurality of contact elements; wherein said substrate is configured for stacking in a stack of substantially identical substrates, wherein said second plurality of contact elements are elongate, compressible spring contacts disposed to be compressed by and thereby form an electrical connection with corresponding ones of said first plurality of contact elements on an adjacent stacked substrate. 22. The stacking substrate of claim 21, wherein said third face is recessed below said first face. 23. The stacking substrate of claim 21, wherein said third face is elevated above said first face. 24. The stacking substrate of claim 21, wherein said first face and said third face are substantially coplanar. 25. The stacking substrate of claim 21, further comprising a stop structure disposed to limit compression of ones of said spring contacts. 26. The stacked semiconductor device assembly of claim 25 further comprising a plurality of said stop structures. 27. A stacked semiconductor device assembly, comprising: a plurality of stacked modules, wherein each of said plurality of stacked modules further comprises at least one semiconductor device mounted to a stacking substrate; first connecting means for connecting each of said at least one semiconductor device to one of the stacking substrates, wherein said first connecting means comprises a first plurality of elongate, compressible spring con
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