[특허]Methods of testing integrated circuitry

[미국특허] Methods of testing integrated circuitry 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G01R-001/073
출원번호	US-0305676 (2002-11-26)
발명자 / 주소	Akram, Salman
출원인 / 주소	Micron Technology, Inc.
대리인 / 주소	Wells St. John P.S.
인용정보	피인용 횟수 : 0 인용 특허 : 29

초록 ▼

A method of testing integrated circuitry includes providing a substrate comprising integrated circuitry to be tested. The circuitry substrate has a plurality of exposed conductive bumps in electrical connection with the integrated circuitry. At least one of the conductive bumps is engaged with an opening of a conductive receptacle at least partially formed in a surface of a test substrate. Thereafter, at least a portion of the receptacle is heated to a temperature greater than 125° C. and within at least 50% in degrees centigrade of and below the melting temperature of the exposed conductive bump effective to deform the engaged bump to be received more fully within the receptacle than initially so received by the engaging. The bumped circuit is tested through the engaged bump deformed within the receptacle. Thereafter, the bump is removed from the receptacle.

대표청구항 ▼

1. A method of testing integrated circuitry comprising: providing a substrate comprising integrated circuitry to be tested, the circuitry substrate having a plurality of exposed conductive bumps in electrical connection with the integrated circuitry; engaging at least one of the conductive bumps with an opening of a conductive receptacle at least partially formed in a surface of a test substrate; after the engaging, heating at least a portion of the receptacle to a temperature greater than 125° C. and within at least 50% in degrees centigrade of and below the melting temperature of the exposed conductive bump effective to deform the engaged bump to be received more fully within the receptacle than initially so received by the engaging; testing the bumped circuit through the engaged bump deformed within the receptacle; and after the testing, removing the engaged bump from the receptacle. 2. The method of claim 1 wherein the heating is to a temperature within at least 30% in degrees centigrade of the melting temperature of the engaged conductive bump. 3. The method of claim 1 wherein the heating is to temperature within at least 20% in degrees centigrade of the melting temperature of the engaged conductive bump. 4. The method of claim 1 wherein the heating is to a temperature not within less than 10% in degrees centigrade of the melting temperature of the engaged conductive bump. 5. The method of claim 1 wherein the testing occurs after lowering temperature of the receptacle from its maximum bump deforming temperature. 6. The method of claim 1 wherein the conductive receptacle has a lateral periphery at said test substrate surface, a conductive resistance heating material being received over said test substrate surface elevationally outward of the respective receptacles and received about at least a portion of the receptacle lateral periphery, conductive engagement material being received within the receptacles; and the heating comprising flowing current through said conductive resistance heating material effective to impart heating thereto. 7. The method of claim 6 wherein the lateral periphery is characterized by at least four substantially straight linear connecting sides, the conductive resistance heating material being received about only three of such sides. 8. The method of claim 6 wherein the conductive resistance heating material comprises polysilicon. 9. The method of claim 6 wherein the conductive resistance heating material comprises polysilicon doped with from 1×1015to 1×1018atoms/cm3. 10. The method of claim 6 wherein the conductive resistance heating material is received only elevationally outward of the receptacle. 11. The method of claim 6 wherein the conductive resistance heating material is received about only a portion of the receptacle lateral periphery. 12. The method of claim 6 wherein the conductive resistance heating material is received only elevationally outward of the receptacle, and is received about only a portion of the receptacle lateral periphery. 13. The method of claim 6 further comprising insulative material received intermediate the conductive engagement material and the conductive resistance heating material.

이 특허에 인용된 특허 (29) 인용/피인용 타임라인 분석

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Koopman Nicholas G. (Raleigh NC) Rinne Glenn A. (Cary NC) Turlik Iwona (Raleigh NC) Yung Edward K. (Carrboro NC), Apparatus for testing, burn-in, and/or programming of integrated circuit chips, and for placing solder bumps thereon.
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Wood Alan G. (Boise ID) Farnworth Warren M. (Nampa ID) Hembree David R. (Boise ID), Carrier for testing an unpackaged semiconductor die.
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Wood Alan G. ; Farnworth Warren M., Carrier having interchangeable substrate used for testing of semiconductor dies.
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Farnworth Warren M. (Nampa ID) Akram Salman (Boise ID) Brooks Mike (Caldwell ID), Carrier having slide connectors for testing unpackaged semiconductor dice.
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Fillion Raymond Albert ; Burdick ; Jr. William Edward, Chip burn-in and test structure and method.
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Kennedy James D., Deflection device.
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Alcoe David James ; Caletka David Vincent, Electronic component test apparatus with rotational probe and conductive spaced apart means.
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Kister January, High temperature probe card for testing integrated circuits.
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Akram Salman (Boise ID) Farnworth Warren M. (Nampa ID) Wood Alan G. (Boise ID), Method for fabricating a self limiting silicon based interconnect for testing bare semiconductor dice.
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Pastore John R. ; Nomi Victor K. ; Wilson Howard P., Method for testing a ball grid array semiconductor device and a device for such testing.
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Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Method of mounting resilient contact structures to semiconductor devices.
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Pope Keith R. (Austin TX) Schrottke Gustav (Austin TX), Non-destructure method of performing electrical burn-in testing of semiconductor chips.
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Higgins H. Dan ; Martinez Martin A. ; Bates R. Dennis, Probe assembly and method for switchable multi-DUT testing of integrated circuit wafers.
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Ikeya Kiyokazu, Socket apparatus particularly adapted for BGA type semiconductor devices.
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A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
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[미국특허] Methods of testing integrated circuitry 원문보기

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