IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0876207
(2001-06-06)
|
우선권정보 |
JP-0171095 (2000-06-07) |
발명자
/ 주소 |
|
출원인 / 주소 |
- NEC Electronics Corporation
|
대리인 / 주소 |
|
인용정보 |
피인용 횟수 :
15 인용 특허 :
7 |
초록
▼
An interlayer insulating film and a first via connected to a diffusion layer in a MOS transistor are formed on the diffusion layer. Then, a low dielectric constant film for a first layer copper interconnection, and the first layer copper interconnection connected to the first via are formed. Then, a
An interlayer insulating film and a first via connected to a diffusion layer in a MOS transistor are formed on the diffusion layer. Then, a low dielectric constant film for a first layer copper interconnection, and the first layer copper interconnection connected to the first via are formed. Then, an etching stopper film, an interlayer insulating film, and a low dielectric constant film for a second layer copper interconnection are formed in this order. Then, a via hole is formed in the etching stopper film and the interlayer insulating film, and a groove is formed in the low dielectric constant film for the second layer copper interconnection. A barrier metal layer is then formed. Thereafter, Ar ions are implanted. At the time, the implantation energy is 50 keV, and the dose is 1×1017cm-2. A second via and the second layer copper interconnection are formed, and annealing is performed at a temperature of 400° C.
대표청구항
▼
An interlayer insulating film and a first via connected to a diffusion layer in a MOS transistor are formed on the diffusion layer. Then, a low dielectric constant film for a first layer copper interconnection, and the first layer copper interconnection connected to the first via are formed. Then, a
An interlayer insulating film and a first via connected to a diffusion layer in a MOS transistor are formed on the diffusion layer. Then, a low dielectric constant film for a first layer copper interconnection, and the first layer copper interconnection connected to the first via are formed. Then, an etching stopper film, an interlayer insulating film, and a low dielectric constant film for a second layer copper interconnection are formed in this order. Then, a via hole is formed in the etching stopper film and the interlayer insulating film, and a groove is formed in the low dielectric constant film for the second layer copper interconnection. A barrier metal layer is then formed. Thereafter, Ar ions are implanted. At the time, the implantation energy is 50 keV, and the dose is 1×1017cm-2. A second via and the second layer copper interconnection are formed, and annealing is performed at a temperature of 400° C. ilm is formed on a surface of a trench formed in the surface of said semiconductor substrate; a conductive material layer for a back gate electrode, which is embedded in a trench of at least one of said element isolation regions, configured to be supplied with a predetermined voltage to make an depletion layer in a region of the semiconductor substrate under the channel region of said MOS transistor; a well region formed in a surface of the supporting semiconductor substrate of said SOI semiconductor substrate, a lower end of said conductive material layer being connected to said well region, and the upper portion of said conductive material layer being covered with the insulating film formed on the surface of said element isolation region. 7. The semiconductor device according to claim 6, further comprising an upper wiring layer which is formed to contact an upper portion of said conductive material layer. 8. The semiconductor device according to claim 7, wherein the upper wiring layer extends onto a peripheral region of the MOS transistor. 9. The semiconductor memory device according to claim 6, wherein said MOS transistor dynamically stores a first data state in which the channel region is set to a first potential and a second data state in which the channel region is set to a second potential, and said first data state is written when an impact-ionization is generated in the vicinity of a drain-channel junction of the MOS transistor, and the second data state is written when a forward bias is applied to the drain-channel junction with a predetermined potential applied thereto by capacity coupling of said gate electrode. 10. A semiconductor device comprising: a memory cell array including an arrangement of MOS transistors for memory cells formed on a semiconductor substrate; a peripheral circuit region formed on said semiconductor substrate; a plurality of trench type element isolation regions formed in the memory cell array and the peripheral circuit region, the element isolation regions having trenches formed in a surface of said semiconductor substrate, and a conductive material layer for a back gate electrode, which is embedded in the trench at least one of the element isolation regions, configured to be supplied with a predetermined voltage to make an depletion layer in a region of the semiconductor substrate under a channel region of the MOS transistor or to voltage-control the semiconductor substrate region. 11. A semiconductor device according to claim 10, wherein said plurality of trench type element isolation regions sandwiches the channel region between said drain and source regions from opposite sides of a channel width direction, and said conductive material layer is embedded in the trench of at least one of the element isolation regions formed on the opposite sides of said channel regions in the channel width direction. 12. The semiconductor device according to claim 10, wherein said conductive material layer is embedded only in the trenches of the element isolation regions formed in said memory cell array. 13. The semiconductor device according to claim 10, further comprising an upper wiring layer which is formed to contact an upper portion of said conductive material layer via a contact. 14. The semiconductor device according to claim 10, wherein said semiconductor substrate is an SOI semiconductor substrate in which a silicon layer is formed on an insulating film formed on a supporting semiconductor substrate. 15. The semiconductor device according to claim 10, wherein said semiconductor substrate is an SOI semiconductor substrate in which a silicon layer is formed on an insulating film formed on a supporting semiconductor substrate, a well region is formed in the surface of the supporting semiconductor substrate of said SOI semiconductor substrate, a lower end of said conductive material layer is connected to said well region, and an upper portion of said conductive material layer is cove red with the insulating film formed on the surface of said element isolation region. 16. The semiconductor device according to claim 15, wherein a contact leading to said well region is formed in a contact region around said memory cell array. 17. The semiconductor memory device according to claim 10, wherein each of said MOS transistors dynamically stores a first data state in which the channel region is set to a first potential and a second data state in which the channel region is set to a second potential, and said first data state is written when an impact-ionization is generated in the vicinity of a drain-channel junction of said each MOS transistor, and the second data state is written when a forward bias is applied between the drain-channel junction with a predetermined potential applied thereto by capacity coupling of said gate electrode of said each MOS transistor. 18. A semiconductor memory device comprising a vertical MOS transistor including: a semiconductor substrate; a first conductive type element region defined in the semiconductor substrate, the element region constituting a channel region; first and second gate electrodes embedded in first and second trenches formed to sandwich the element region, the first and second gate electrodes opposing to side surfaces of the element region; first and second gate insulation films provided between the first gate electrode and the element region and the second gate electrode and the element region, respectively; a second conductive type drain diffusion layer formed on a surface of said element region; and a second conductive type source diffusion layer embedded in semiconductor substrate in a predetermined depth. 19. The semiconductor memory device according to claim 18, wherein a plurality of said MOS transistor are defined by element isolation insulating films and arranged in a matrix, the source diffusion layer is common to the MOS transistor arranged in the matrix, the drain diffusion layers of the MOS transistor arranged in a first direction are connected to a bit line, the first gate electrodes of the MOS transistor arranged in a second direction intersecting the first direction are connected to a word line, and the second gate electrodes of the MOS transistor arranged in the second direction are connected to a back word line. 20. The semiconductor memory device according to claim 19, wherein said back word line is driven in synchronization with the word line to control a potential of the element region. 21. The semiconductor memory device according to claim 19, wherein in a bit line direction, first and second trenches are formed at opposite ends of each of the element forming region and a third trench is formed at a middle portion thereof to separate the element forming region in the bit line direction, the first and second gate electrodes are embedded in the first and second trenches, respectively, a third gate electrode is embedded in the third trench, and the third gate electrode constitutes a common gate electrode of the is separated element forming regions. 22. The semiconductor memory device according to claim 21, wherein said back word line connected to the third gate electrode constitutes a common back word line of the separated element forming regions in the bit line direction, and a fixed potential is applied to the third gate electrode so that side surfaces of the third gate electrode are kept in majority carrier accumulated state. 23. The semiconductor memory device according to claim 18, wherein the first and second trenches are formed at opposite ends of the element region in a bit line direction, and the first and second gate electrodes are embedded in the trenches. 24. The semiconductor memory device according to claim 18, wherein said element region of the MOS transistor is electrically floating. 25. The semiconductor memory device according to claim 18, wherein said MOS transistor dynamically stores a first data state in which the ele
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