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The invention includes a method of forming a semiconductor construction. A first substrate is provided which comprises silicon-containing structures separated from one another by an insulative material. The silicon-containing structures define an upper surface. A second semiconductor substrate is pr

The invention includes a method of forming a semiconductor construction. A first substrate is provided which comprises silicon-containing structures separated from one another by an insulative material. The silicon-containing structures define an upper surface. A second semiconductor substrate is provided which comprises a monocrystalline material having a damage region therein. The second semiconductor substrate is bonded to the silicon-containing structures of the first substrate at the upper surface. The monocrystalline material is then cleaved along the damage region. The invention also encompasses a semiconductor construction comprising a first substrate having silicon-containing structures separated from one another by an insulative material, and a second substrate comprising a monocrystalline material. The silicon-containing structures of the first substrate define an upper surface, and the monocrystalline material of the second substrate is bonded over the silicon-containing structures at the upper surface.

대표청구항 ▼

The invention includes a method of forming a semiconductor construction. A first substrate is provided which comprises silicon-containing structures separated from one another by an insulative material. The silicon-containing structures define an upper surface. A second semiconductor substrate is pr

The invention includes a method of forming a semiconductor construction. A first substrate is provided which comprises silicon-containing structures separated from one another by an insulative material. The silicon-containing structures define an upper surface. A second semiconductor substrate is provided which comprises a monocrystalline material having a damage region therein. The second semiconductor substrate is bonded to the silicon-containing structures of the first substrate at the upper surface. The monocrystalline material is then cleaved along the damage region. The invention also encompasses a semiconductor construction comprising a first substrate having silicon-containing structures separated from one another by an insulative material, and a second substrate comprising a monocrystalline material. The silicon-containing structures of the first substrate define an upper surface, and the monocrystalline material of the second substrate is bonded over the silicon-containing structures at the upper surface. ric layer on the bottom of the opening; forming a floating gate on the sidewall of the opening, wherein the top of the floating gate is lower than a surface of the mask layer; forming a source region in the substrate exposed by the opening using the floating gate serving as a mask; forming an inter-gate dielectric layer in the opening; forming a control gate filled in the opening; removing the mask layer; forming a gate dielectric layer on the substrate and forming spacers on the side wall of the floating gate and the control gate; forming a select gate on the sidewall of the spacers; and forming a drain region in the substrate on one side of the select gate. 2. The method of fabricating a flash memory of claim 1, wherein the step of forming the floating gate on the sidewall of the opening comprises: forming a first conducting layer over the substrate; removing a part of the first conducting layer by an anisotropic etching process to form a first conducting spacer on the sidewall of the opening, wherein the top of the first conducting spacer is lower than the surface of the mask layer; and patterning the first conducting spacer to form the floating gate. 3. The method of fabricating a flash memory of claim 1, wherein the step of forming the control gate filled in the opening comprises: forming a second conducting layer over the substrate; and removing the second conducting layer beside the opening to form the control gate. 4. The method of fabricating a flash memory of claim 3, wherein the second conducting layer besides the opening is removed by etching back. 5. The method of fabricating a flash memory of claim 3, wherein the second conducting layer besides the opening is removed by a chemical mechanical polishing process. 6. The method of fabricating a flash memory of claim 1, wherein the step of forming the select gate on the sidewall of the spacers comprises: forming a third conducting layer over the substrate; and removing the third conducting layer by an anisotropic etching process to form the select gate on the sidewall of the spacers. 7. The method of fabricating a flash memory of claim 6, wherein the mask layer comprises a silicon nitride layer. 8. The method of fabricating a flash memory of claim 1, wherein the gate dielectric layer comprises a silicon oxide/silicon nitride/silicon oxide stacked layer. 9. The method of fabricating a flash memory of claim 1, wherein the pad layer comprises a silicon oxide layer. 10. The method of fabricating a flash memory of claim 1, wherein the material of the mask layer has an different etching selectivity with the floating gate, the control gate and the select gate. 11. A method of fabricating a flash memory, comprising: providing a substrate and an isolation region formed thereon to define an active region; forming a pad layer on the active region of the substrate; forming a mask layer over the substrate; patterning the mask layer and forming an opening therein; removing the pad layer exposed by the opening; forming a tunneling dielectric layer on the bottom of the opening; forming a first conducting layer over the substrate; removing a part of the first conducting layer by an anisotropic etching process to form a first conducting spacer on the sidewall of the opening, wherein the top of the first conducting spacer is lower than the surface of the mask layer; patterning the first conducting spacer to form a floating gate; forming a source region in the substrate exposed by the opening using the floating gate serving as a mask; forming an inter-gate dielectric layer in the opening; forming a second conducting layer over the substrate; removing the second conducting layer beside the opening to form a control gate; removing the mask layer; forming a gate dielectric layer on the substrate and forming spacers on the side wall of the floating gate and the control gate; forming a third conducting layer over the substrate; removing the thir