IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0672668
(2000-09-28)
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발명자
/ 주소 |
|
출원인 / 주소 |
- National Semiconductor Corporation
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
21 인용 특허 :
6 |
초록
▼
An image sensing pixel cell includes a reset circuit, a capacitance, a photodiode, an amplifier circuit, and a voltage buffer. The reset circuit couples an initial voltage to a first node at an initial time, where the capacitance stores the initial voltage. The amplifier circuit is arranged to bias
An image sensing pixel cell includes a reset circuit, a capacitance, a photodiode, an amplifier circuit, and a voltage buffer. The reset circuit couples an initial voltage to a first node at an initial time, where the capacitance stores the initial voltage. The amplifier circuit is arranged to bias the photodiode at a relatively constant voltage. The voltage buffer circuit buffers the first node to produce a second voltage that corresponds to the voltage at the first node at a subsequent time. The second voltage is different from the initial voltage when a photocurrent flows in the photodiode. A pixel cell may include a shutter circuit having a closed position and an open position. The shutter circuit provides a conductive path for the photocurrent between the photodiode and a power supply connection when in the closed position. The shutter circuit provides another conductive path for the photocurrent between the photodiode and the first node when in the open position. In operation, every pixel cell in the array is reset at substantially the same time. The shutter opens for the entire pixel array to allow photocurrents to integrate on the capacitors in each pixel cell. The shutter closes and image data is read from the array of pixel cells. The image data for an image corresponds to the integrated photocurrents stored on the capacitors in the array of pixel cells.
대표청구항
▼
An image sensing pixel cell includes a reset circuit, a capacitance, a photodiode, an amplifier circuit, and a voltage buffer. The reset circuit couples an initial voltage to a first node at an initial time, where the capacitance stores the initial voltage. The amplifier circuit is arranged to bias
An image sensing pixel cell includes a reset circuit, a capacitance, a photodiode, an amplifier circuit, and a voltage buffer. The reset circuit couples an initial voltage to a first node at an initial time, where the capacitance stores the initial voltage. The amplifier circuit is arranged to bias the photodiode at a relatively constant voltage. The voltage buffer circuit buffers the first node to produce a second voltage that corresponds to the voltage at the first node at a subsequent time. The second voltage is different from the initial voltage when a photocurrent flows in the photodiode. A pixel cell may include a shutter circuit having a closed position and an open position. The shutter circuit provides a conductive path for the photocurrent between the photodiode and a power supply connection when in the closed position. The shutter circuit provides another conductive path for the photocurrent between the photodiode and the first node when in the open position. In operation, every pixel cell in the array is reset at substantially the same time. The shutter opens for the entire pixel array to allow photocurrents to integrate on the capacitors in each pixel cell. The shutter closes and image data is read from the array of pixel cells. The image data for an image corresponds to the integrated photocurrents stored on the capacitors in the array of pixel cells. controlled by said signal controller. 5. The wafer holder as claimed in claim 1, wherein said wafer holder comprises a susceptor. 6. The wafer holder as claimed in claim 1, wherein said wafer holder comprises a pedestal. 7. The wafer holder of claim 1, further comprising a holder base that is positioned under the wafer, each of said temperature sensors having an exposed portion that extends above said holder base to support the wafer and a buried portion that is embedded within said holder base. 8. The wafer holder of claim 7, wherein said temperature sensors are radially arrayed from a center of said holder base and spaced apart to detect temperatures at different radially arrayed points of the wafer. 9. A lamp anneal apparatus comprising: a chamber; a wafer holder accommodated in said chamber for holding a wafer to be annealed; a first set of lamps provided over a top wall of said chamber; and a second set of lamps provided under a bottom wall of said chamber, wherein said wafer holder has a plurality of contact temperature sensors which are positioned under the wafer so that said contact temperature sensors receive substantially no radiation from lamps, and said contact temperature sensors are in contact with a bottom surface of said wafer for supporting all of said wafer's weight and detecting temperatures at different points of said wafer. 10. The lamp anneal apparatus as claimed in claim 9, wherein said contact temperature sensors are electrically connected through a controller to said lamps to transmit signals indicating detected temperatures to said controller so that power to be supplied to said lamps is controlled by said controller on the basis of said signals from said contact temperature sensors. 11. The lamp anneal apparatus as claimed in claim 10, wherein said controller independently controls individual power to be supplied to said lamps on the basis of individual signals from said contact temperature sensors which individually detect temperatures of said wafer at individual points onto which said lamps individually radiate. 12. The lamp anneal apparatus as claimed in claim 11, wherein said controller comprises a signal controller connected through signal transmission lines to said contact temperature sensors for controlling signals, and a power controller connected to said signal controller and also connected through power transmission lines to said lamps for controlling power to be supplied through said power transmission lines to said lamps on the basis of signals controlled by said signal controller. 13. The lamp anneal apparatus as claimed in claim 9, wherein said wafer holder comprises a susceptor. 14. The lamp anneal apparatus as claimed in claim 9, wherein said wafer holder comprises a pedestal. 15. The lamp anneal apparatus as claimed in claim 9, wherein said lamps of said first set are rod-shaped and aligned in parallel to each other within a single plane parallel to said top wall of said chamber. 16. The lamp anneal apparatus as claimed in claim 9, wherein said lamps of said second set are rod-shaped and aligned in parallel to each other within a single plane parallel to said top wall of said chamber. 17. The lamp anneal apparatus as claimed in claim 9, wherein said lamps of said first set are rod-shaped and said alignment structure comprises a first level alignment and a second level alignment over said first level alignment, said first level alignment aligns said lamps extend in parallel to each other within a first level plane parallel to said top wall of said chamber so that said lamps extends in a first direction included in said first level plane, and said second level alignment aligns said lamps in parallel to each other within a second level plane parallel to said top wall of said chamber so that said lamps extends in a second direction perpendicular to said first direction and included in said second level plane to form a multi-level meshed structure of said lamps. 18. The lamp anne al apparatus of claim 9, wherein said wafer holder comprises a holder base that is positioned under the wafer, each of said temperature sensors having an exposed portion that extends above said holder base to support the wafer and a buried portion that is embedded within said holder base. 19. The lamp anneal apparatus of claim 18, wherein said temperature sensors are radially arrayed from a center of said holder base and spaced apart to detect temperatures at different radially arrayed points of the wafer. 20. A lamp anneal apparatus comprising: a chamber; a wafer holder accommodated in said chamber for holding a wafer to be annealed, wherein said wafer holder has a plurality of contact temperature sensors which are positioned under the wafer so that said contact temperature sensors receive substantially no radiation from lamps, and said contact temperature sensors are in contact with a bottom surface of said wafer for supporting all of said wafer's weight and detecting temperatures at different points of said wafer; a first set of lamps provided over a top wall of said chamber, wherein said lamps of said first set are rod-shaped and aligned in parallel to each other within a single plane parallel to said top wall of said chamber; and a second set of lamps provided under a bottom wall of said chamber, wherein said contact temperature sensors are electrically connected through a controller to said lamps to transmit signals indicating detected temperatures to said controller so that power to be supplied to said lamps are controlled by said controller on the basis of said signals from said contact temperature sensors, and said controller independently controls individual power to be supplied to said lamps on the basis of individual signals from said contact temperature sensors which individually detect temperatures said wafer at individual points onto which said lamps individually radiate. 21. The lamp anneal apparatus as claimed in claim 20, wherein said controller comprises a signal controller connected through signal transmission lines to said contact temperature sensors for controlling signals, and a power controller connected to said signal controller and also connected through power transmission lines to said lamps for controlling powers to be supplied through said power transmission lines to said lamps on the basis of signals controlled by said signal controller. 22. The lamp anneal apparatus as claimed in claim 20, wherein said wafer holder comprises a susceptor. 23. The lamp anneal apparatus as claimed in claim 20, wherein said wafer holder comprises a pedestal. 24. The lamp anneal apparatus of claim 20, wherein said wafer holder comprises a holder base that is positioned under the wafer, each of said temperature sensors having an exposed portion that extends above said holder base to support the wafer and a buried portion that is embedded within said holder base. 25. The lamp anneal apparatus of claim 24, wherein said temperature sensors are radially arrayed from a center of said holder base and spaced apart to detect temperatures at different radially arrayed points of the wafer. 26. A lamp anneal apparatus comprising: a chamber; a wafer holder accommodated in said chamber for holding a wafer to be annealed, wherein said wafer holder has a plurality of contact temperature sensors which are positioned under the wafer so that said contact temperature sensors receive substantially no radiation from lamps, and said contact temperature sensors are in contact with a bottom surface of said wafer for supporting all of said wafer's weight and detecting temperatures at different points of said wafer; a first set of lamps provided over a top wall of said chamber, wherein said lamps of said first set are rod-shaped and said alignment structure comprises a first level alignment and a second level alignment over said first level alignment, said first level alignment aligns said lamps in parallel to each other within a
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