초록 ▼

A computer-assisted method for presenting a multi-media plurality of elements. Each element, including, for example, video images, still images and documents, is stored by assigned index number in an appropriate input device such as a VHS recorder or laser disk reader (video and stills) or an optica

A computer-assisted method for presenting a multi-media plurality of elements. Each element, including, for example, video images, still images and documents, is stored by assigned index number in an appropriate input device such as a VHS recorder or laser disk reader (video and stills) or an optical or magnetic disk reader (documents). The input devices are addressed by such index numbers to thereby call up and display selected elements in a WINDOWS format. The format is adjustable from a basic default setting to enable the user to customize frames prior to entry into a script buffer. Thereafter the script buffer is addressable, permitting the frames constituting the presentation to be entered into a script file in a preferred presentation sequence. The presentation is made by addressing the script file to recall selected frames. The method allows the user to preview flames one at a time and allows the user to reformat each frame prior to public display.

대표청구항 ▼

A computer-assisted method for presenting a multi-media plurality of elements. Each element, including, for example, video images, still images and documents, is stored by assigned index number in an appropriate input device such as a VHS recorder or laser disk reader (video and stills) or an optica

A computer-assisted method for presenting a multi-media plurality of elements. Each element, including, for example, video images, still images and documents, is stored by assigned index number in an appropriate input device such as a VHS recorder or laser disk reader (video and stills) or an optical or magnetic disk reader (documents). The input devices are addressed by such index numbers to thereby call up and display selected elements in a WINDOWS format. The format is adjustable from a basic default setting to enable the user to customize frames prior to entry into a script buffer. Thereafter the script buffer is addressable, permitting the frames constituting the presentation to be entered into a script file in a preferred presentation sequence. The presentation is made by addressing the script file to recall selected frames. The method allows the user to preview flames one at a time and allows the user to reformat each frame prior to public display. cceeding inverting cell of the cascaded inverting cells (14, 15, 16) having an input connected to receive an output signal (ext, ext') derived from a preceding inverting cell, the output signal (ext, ext') being connected to a control circuit (17, 18) having a control signal applied thereto for controlling a temporal profile of the output signal (ext, ext'), the input of the first inverting cell (16) being connected to receive an output of the last cell (15) of the cascaded inverting cells, at least one inverting cell (14, 15) being constituted by a cell having a gain that is variable as a function of the control signal (contr, contr') applied to said at least one inverting cell (14, 15) for causing the output signal (ext ext') from said at least one inverting cell (14, 15) to remain substantially in its current logic state for a certain length of time after which the output signal (ext, ext') from said at least one inverting cell abruptly (14, 15) changes to a logic state with a steep leading edge at the output of said at least one inverting cell (14, 15) for a change in logic state at the input of said at least one inverting cell (14, 15). .. 4. The variable frequency oscillator according to claim 3 wherein the variable gain cell comprises: an inverting amplifier (1, 2) fed by a high-potential node (6) and a low-potential node (5), the output of which is constituted by an output node (4), a first transistor (3) having a source, drain and gate, the source being connected to a fixed potential lower than the potential of the low-potential node (5), the drain being connected to the low-potential node (5) and the gate being at the potential of the control signal (contr) in analog form, and a second transistor (12) having a source, drain and gate, the drain being connected to a fixed potential higher than the potential of the high-potential node (6), the source being connected to the low-potential (5) and the gate being at the potential of the output node (4) such that the second transistor (12) conducts a current when the output node (4) is at a potential higher than the low-potential node (5). .. 5. The variable frequency oscillator according to claim 3 wherein the variable gain cell comprises: an inverting amplifier (1, 2) fed by a high-potential node (6) and a low-potential node (5), the output of which is constituted by an output node (4), a first transistor (7) having a source, drain and gate, the source being connected to a fixed potential higher than the potential of the high-potential node (6) and the drain being connected to the high-potential node (6) and the gate being at the potential of the control signal (contr) in analog form, and a second transistor (11) having a source, drain and gate, the drain connected to a fixed potential lower than the potential of the low-potential node (5), the source being connected to the high-potential node (6) and the gate being at the potential of the output node (4) such that the second transistor (11) conducts a current when the output node (4) is at a potential lower than the high-potential node (6). .. 6. The variable frequency oscillator according to claim 4 wherein the variable gain cell further comprises: a third transistor (7) having a source, drain and gate, the source being connected to a fixed potential higher than the potential of the high-potential node (6) and the drain being connected to the high-potential node (6) and the gate being at the potential of the control signal (contr) in analog form, and a fourth transistor (11) having a source, drain and gate, the drain connected to a fixed potential lower than the potential of the low-potential node (5), the source being connected to the high-potential node (6) and the gate being at the potential of the output node (4) such that the fourth transistor (11) conducts a current when the output node (4) is at a potential lower than the high-potential node (6). .. 7. The variable frequency oscillator accor ding to claim 3 wherein the variable gain cell comprises: an inverting amplifier (1, 2) connected to be fed by a high-potential node (6) and a low-potential node (5), the output of which is constituted by an output node (4), a first plurality of transistors (31, 32, 33, 34) each having a source, drain and gate, the sources being connected to a fixed potential lower than the potential of the low-potential node (5), the drains being connected to the low-potential node (5) and each of whose rates is at a high or low potential of a bit of the control signal (contr) in digital form, and a second transistor (12) having a source, drain and gate, the drain being connected to a fixed potential higher than the potential of the high-potential node (6), the source being connected to the low-potential node (5) and the gate being at the potential of the output node (4). .. 8. The variable frequency oscillator according to claim 3 wherein the variable gain cell comprises: an inverting amplifier (1, 2) connected to be fed by a high-potential node (6) and a low-potential node (5), the output of which is constituted by an output node (4), a first plurality of transistors (71, 72, 73, 74) each having a source, drain and gate, the sources being connected to a fixed potential higher than the potential of the high-potential node (6), the drains being connected to the high-potential node (6) and each of whose gates is adapted to be connected to receive an inverted low- or high-potential of a bit of the control signal (contr) in digital form, and a second transistor (11) having a source, drain and gate, the drain being connected to a fixed potential lower than the potential of the low-potential node (5), the source being connected to the high-potential node (6) and the gate being at the potential of the output node (4). .. 9. The variable frequency oscillator according to claim 7, wherein the variable gain cell further comprises: a third plurality of transistors (71, 72, 73, 74) each having a source, drain and gate, the sources being connected to a fixed potential higher than the potential of the high-potential node (6), the drains being connected to the high-potential node (6) and each of whose gates is adapted to be connected to receive an inverted low- or high-potential of a bit of the control signal (contr) in digital form, and a fourth transistor (11) having a source, drain and gate, the drain being connected to a fixed potential lower than the potential of the low-potential node (5), the source being connected to the high-potential node (6) and the gate being at the potential of the output node (4). .. 10. A cell for obtaining an output signal (ext) with a variable delay τ in response to an input signal (inp), the output signal (ext, ext') being connected to a control circuit having a control signal applied thereto for controlling a temporal profile of the output signal (ext), comprising: an inverting amplifier having a gain controlled by a control signal (contr, contr'), wherein the output signal (ext) is inversely related to the value of the gain so as to cause the output signal (ext, ext') to remain substantially in its current logic state for a certain length of time after which the output signal (ext,ext') changes its logic state with a magnitude that is a function of the control signal (contr, contr') after a change of state of the input signal (inp). .. 11. The cell according to claim 10, further comprising: the inverting amplifier (1, 2) being connected to be fed by a high-potential node (6) and a low-potential node (5), and having an output node (4) for supplying an output signal (ext), a first transistor (3) having a source, drain and gate, the source connected to a fixed potential lower than the potential of the low-potential node (5) the drain being connected to the low-potential node (5), and the gate adapted to be maintained at the potential of the control signal (contr) in analog form, and a se cond transistor (12) having a drain, source and gate, the drain being connected to a fixed potential higher than the potential of the high-potential node (6), the source being connected to the low-potential node (5) and the gate being at the potential of the output node (4) such that the second transistor (12) conducts a current when the output node (4) is at a potential higher than the low-potential node (5). .. 12. The cell according to claim 10 further comprising: the inverting amplifier (1, 2) being connected to be fed by a high-potential node (6) and a low-potential node (5), and having an output node (4) for supplying an output signal (ext), a first transistor (7) having a source, drain and gate, the source being connected to a fixed potential greater than the potential of the high-potential node (6), the drain being connected to the high-potential node (6) and the gate being at the potential of the control signal (contr) in analog form, and a second transistor (11) having a source, drain and gate, the drain being connected to a fixed potential lower than the potential of the low-potential node (5), the source being connected to the high-potential node (6) and the gate being at the potential of the output node (4) such that the second transistor (11) conducts a current when the output node (4) is at a potential lower than the high-potential node (6). .. 13. The cell according to claim 11 further comprising: a third transistor (7) having a source, drain and gate, the source being connected to a fixed potential greater than the potential of the high-potential node (6) and the drain being connected to the high-potential node (6) and the gate being at the potential of the control signal (contr) in analog form, and a fourth transistor (11) having a source, drain and gate, the drain connected to a fixed potential lower than the potential of the low-potential node (5), the source being connected to the high-potential node (6) and the gate being at the potential of the output node (4) such that the fourth transistor (11) conducts a current when the output node (4) is at a potential lower than the high-potential node (6). .. 14. The cell according to claim 10 further comprising: the inverting amplifier (1, 2) being fed by a high-potential node (6) and a low-potential node (5), and having an output node (4) for supplying an output signal (ext), a first plurality of transistors (31, 32, 33, 34) each having a source, drain and gate, the sources being connected to a fixed potential lower than the potential of the low-potential node (5), the drains being connected to the low-potential node (5) and each gate being at a high- or low-potential of a bit of the control signal (contr) in digital form, and a second transistor (12) having a source, drain and gate, the drain being connected to a fixed potential higher than the potential of the high-potential node (6), the source being connected to the low-potential node (5) and the gate being at the potential of the output node (4). .. 15. A cell according to claim 10, further comprising: the inverting amplifier (1, 2) being fed by a high-potential node (6) and a low-potential node (5), and having an output node (4) for supplying an output signal (ext), a first plurality of transistors (71, 72, 73, 74) each having a source, drain and gate, the sources being connected to a fixed potential higher than the potential of the high-potential node (6), the drains being connected to the high-potential node (6), and each of the gates is adapted to receive an inverted low- or high-potential of a bit of the control signal (contr) in digital form, and a second transistor (11) having a source, drain and gate, the drain being connected to a fixed potential lower than the potential of the low-potential node (5), the source being connected to the high-potential node (6) and the being at the potential of the output node (4). .. 16. A cell according to claim 14, further comprisi ng: a third plurality of transistors (71, 72, 73, 74) each having a source, drain and gate, the sources being connected to a fixed potential higher than the potential of the high-potential node (6), the drains being connected to the high-potential node (6), and each of the gates is adapted to receive an inverted low- or high-potential of a bit of the control signal (contr) in digital form, and a fourth transistor (11) having a source, drain and gate, the drain being connected to a fixed potential lower than the potential of the low-potential node (5), the source being connected to the high-potential node (6) and the gate being at the potential of the output node (4). 17. A ring oscillator having a variable frequency controlled by an analog control signal, comprising an odd number of cascaded inverting gates, each inverting gate having an input connected to receive an input signal which, except for the first of the cascaded inverting gates, corresponds to an output signal derived from a preceding inverting gate, the input of the first inverting gate being connected to receive the output signal of the last inverting gate, and at least one inverting gate being constituted by a cell having a gain that is variable as a function of the analog control signal for causing the output signal to remain substantially in its current logic state for a certain length of time after which the output signal abruptly changes to a logic state with a steep leading edge at the output of said at least one inverting gate in response to predetermined steep edges at the input of said at least one inverting gate, the cell including: one inverter connected between a high-potential node and a low-potential node and having an input connected to receive said input signal and an output node providing said output signal, a first N-type transistor having a drain connected to said low-potential node, a source connected to a first fixed potential lower than the potential of said low-potential node, and a gate connected to receive the analog control signal, and a second N-type transistor having a drain connected to a second fixed potential equal or higher than the potential of said high-potential node, a source connected to said low-potential node and a gate connected to said output node. 18. A ring oscillator according to claim 17, wherein the cell further includes: a first P-type transistor having a drain connected to said high-potential node, a source connected to said second fixed potential and a gate connected to receive a signal varying inversely to the analog control signal, and a second P-type transistor having a drain connected to said first fixed potential, a source connected to said high-potential node and a gate connected to said output node. 19. A ring oscillator having a variable frequency controlled by an analog control signal, comprising an odd number of cascaded inverting gates, each inverting gate having an input connected to receive an input signal which, except for the first of the cascaded inverting gates, corresponds to an output signal derived from a preceding inverting gate, the input of the first inverting gate being connected to receive the output signal of the last inverting gate, and at least one inverting gate being constituted by a cell having a gain that is variable as a function of the analog control signal for causing the output signal to remain substantially in its current logic state for a certain length of time after which the output signal abruptly changes to a logic state with a steep leading edge at the output of said at least one inverting gate in response to predetermined steep edges at the input of said at least one inverting gate, the cell including: one inverted connected between a high-potential node and a low-potential node and having an input connected to receive said input signal and an output node providing said output signal, a first P-type transistor having a drain connected to