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A method and apparatus for generating multiple ultra-fast (picosecond-range) electrical sampling apertures and pulses in response to a slewed control signal is disclosed. In one embodiment a series or sequence of sampling apertures are formed for sampling an input signal without the use of delay lines. In another embodiment, the input to be sampled is incrementally delayed to generate signals along a delay line. The delayed signals are simultaneously sampled in a sampling window to obtain a group of samples of an input signal at the same time. In another...
A method and apparatus for generating multiple ultra-fast (picosecond-range) electrical sampling apertures and pulses in response to a slewed control signal is disclosed. In one embodiment a series or sequence of sampling apertures are formed for sampling an input signal without the use of delay lines. In another embodiment, the input to be sampled is incrementally delayed to generate signals along a delay line. The delayed signals are simultaneously sampled in a sampling window to obtain a group of samples of an input signal at the same time. In another embodiment, a series or sequence of ultra-fast pulses are formed in an output signal without using delay lines. Parallel and serial sampler/pulser circuitry are disclosed. differential amplification component between the two pulse signals as the PWM signal, wherein said pulse generator varies pulse width of a first of the two pulse signals, on a bit-by-bit basis, of the basic clock pulse train, in response to the value of the digital input data, and holds a level of a second of the two pulse signals throughout the bits of the basic clock pulse train. 10. A pulse width modulation (PWM) converting method PWM converting each value of digital input data for each bit of a basic clock pulse train, and outputs a conversion result as a PWM signal, said PWM converting method comprising: generating two pulse signals, asserting one having a low level and one having a high level for each bit of a basic clock pulse train, in response to value of digital input data; varying a pulse width of a first of the two pulse signals, on a bit-by-bit basis, of the basic clock pulse train, in response to the value of the digital input data; holding a level of a second of the two pulse signals throughout the bits of the basic clock pulse train; and outputting a differential amplification component between the two pulse signals as the PWM signal. 970600, Iwama, 362/083.1; US-5644851, 19970700, Blank et al., 033/361; US-5649758, 19970700, Dion, 362/103; US-5661455, 19970800, Van Lente et al., 340/525; US-5669698, 19970900, Veldman et al., 362/083.1; US-5671996, 19970900, Bos et al., 362/083.1; US-5691848, 19971100, Van Lente et al., 359/601; US-5699044, 19971200, Van Lente et al., 340/525; US-5708410, 19980100, Blank et al., 350/438; US-5708415, 19980100, Van Lente et al., 340/525; US-5724187, 19980300, Varaprasad et al., 359/608; US-5737226, 19980400, Olson et al., 364/457; US-5786772, 19980700, Schofield et al., 340/903; US-5796094, 19980800, Schofield et al., 250/208.1; US-5798575, 19980800, O'Farrell et al., 307/010.1; US-5802727, 19980900, Blank et al., 033/361; US-5808197, 19980900, Dao, 073/514.09; US-5820097, 19981000, Spooner, 248/549; US-5910854, 19990600, Varaprasad et al., 359/273; US-5971552, 19991000, O'Farrell et al, 359/871; US-6087953, 20000700, DeLine et al., 340/815.4; US-6124886, 20000900, DeLine et al., 348/148; US-6166625, 20001200, Teowee et al., 340/426; US-6172613, 20010100, DeLine et al., 340/815.4; US-6198409, 20010300, Schofield et al., 340/903; US-6222460, 20010400, DeLine et al., 340/815.4; US-6326900, 20011200, DeLine et al., 340/815.4; US-6366213, 20020400, DeLine et al., 350/815.4