IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0942444
(2001-08-30)
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발명자
/ 주소 |
- Jacomb-Hood, Anthony Wykeham
- Volman, Vladimir
- Lier, Erik
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출원인 / 주소 |
- Lockheed Martin Corporation
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대리인 / 주소 |
Scully, Scott, Murphy & Presser
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인용정보 |
피인용 횟수 :
10 인용 특허 :
6 |
초록
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A means and method to increase the beam traffic capacity, especially in high user density regions, of a multi-beam antenna communication system with multiple signals at any frequency transmitted (received) when in a transmit (receive) mode by canceling interference with neighboring signals. An inter
A means and method to increase the beam traffic capacity, especially in high user density regions, of a multi-beam antenna communication system with multiple signals at any frequency transmitted (received) when in a transmit (receive) mode by canceling interference with neighboring signals. An interference cancellation network is provided for canceling the interference caused by the sidelobe(s) of at least one signal with one or more of the other signals in the network. Each power divider divides its input signal into one reference fractional signal and at least one non-reference fractional signal. Phase shifters/attenuators shift the phase and attenuate the amplitude of at least one of the non-reference fractional signals. Each power combiner combines its input reference fractional signal with at least one non-reference fractional signal into a composite signal emerging from the combiner. The phase/attenuation settings are selected to optimize the signal to interference ratio for each communications link.
대표청구항
▼
A means and method to increase the beam traffic capacity, especially in high user density regions, of a multi-beam antenna communication system with multiple signals at any frequency transmitted (received) when in a transmit (receive) mode by canceling interference with neighboring signals. An inter
A means and method to increase the beam traffic capacity, especially in high user density regions, of a multi-beam antenna communication system with multiple signals at any frequency transmitted (received) when in a transmit (receive) mode by canceling interference with neighboring signals. An interference cancellation network is provided for canceling the interference caused by the sidelobe(s) of at least one signal with one or more of the other signals in the network. Each power divider divides its input signal into one reference fractional signal and at least one non-reference fractional signal. Phase shifters/attenuators shift the phase and attenuate the amplitude of at least one of the non-reference fractional signals. Each power combiner combines its input reference fractional signal with at least one non-reference fractional signal into a composite signal emerging from the combiner. The phase/attenuation settings are selected to optimize the signal to interference ratio for each communications link. sponding one of elements yn, wherein each element of sequence ynis generated at step e by an m-bit analog-to-digital converter in response to its corresponding element of sequence bn,and wherein step f comprises the substeps of: f1. generating a sequence of elements fn,each representing the quantization error difference between magnitudes represented by a concurrently occurring pair of elements bnand yn; and f2. filtering the fnsequence to produce the rnsequence. 7. The method in accordance with claim 1 wherein each of elements xn,an,bn,cn,and rnis a digital data word. 8. The method in accordance with claim 7 wherein each of elements is generated at step e by a digital quantizer in response to a separate one of elements bn. 9. The method in accordance with claim 8 wherein step f comprises the substeps of: f1. generating a sequence of elements fn,each representing the quantization error difference between magnitudes represented by a concurrently occurring pair of elements bnand yn; and f2. filtering the fnsequence to produce the rnsequence. 10. The method in accordance with claim 7 further comprising the step of: g. processing the sequence of elements ynto produce a sequence D consisting of every kth element Dnof a sequence where N1 and N2 are integers and f-N1through fN2are a real numbers. 11. An apparatus for processing a sequence of elements xn,each representing a magnitude, the apparatus comprising: first means for providing a sequence of elements cnin response to a sequence of elements yn,wherein elements ynare m-bit data words representing magnitudes with m-bit resolution, wherein concurrently occurring elements cnand ynrepresent similar magnitudes; second means for generating a sequence of elements anin response to the sequences of elements xnand cn,wherein each element anrepresents a magnitude proportional to a difference between magnitudes represented by a separate concurrently occurring pair of elements xnand cn; third means for filtering the sequence of elements anto produce a sequence of elements dn; fourth means for generating a sequence of elements bnin response to the sequence of elements dnand a sequence of elements rn,wherein each element bnrepresents with at least p-bit resolution a magnitude proportional to a difference between magnitudes represented by a separate concurrently occurring pair of elements dnand rn,wherein m and p are integers and, wherein p>m>0, fifth means for generating the sequence of elements ynin response to the sequence of elements bn,wherein each element yncorresponds to a separate one of elements bnand represents with m-bit resolution a same magnitude its corresponding element bnrepresents with at least p-bit resolution; and sixth means for generating the sequence of elements rnwherein each element rnsequence represents a magnitude proportional to a quantization error difference between magnitudes represented by a separate corresponding pair of elements bnand yn. 12. The apparatus in accordance with claim 11 wherein the sixth means comprises: seventh means for generating a sequence of elements fn,wherein each element fnrepresents a quantization error difference between magnitudes represented by a corresponding pair of elements bnand yn; and eighth means for filtering the fnsequence to produce the rnsequence. 13. The apparatu s in accordance with claim 11 wherein elements xn,an,bn,cn,and rncomprise discrete analog signal levels. 14. The apparatus in accordance with claim 11 wherein the first means comprises an m-bit digital-to-analog converter for converting each element yninto a corresponding one of elements cn. 15. The apparatus in accordance with claim 11 wherein the second means comprises an m-bit analog-to-digital converter for generating each element ynin response to a corresponding one of elements bn. 16. The apparatus in accordance with claim 11 wherein each of elements xn,an,bn,cn,and rnis a digital data word. 17. The apparatus in accordance with claim 11 wherein the fifth means comprises a digital quantizer for generating each of elements ynin response to a corresponding one of elements bn. 18. The apparatus in accordance with claim 15 further comprising: an m-bit digital-to-analog converter for converting the sequence of elements yninto a first analog signal. 19. The apparatus in accordance with claim 18 further comparing: a low pass filter for filtering the first analog signal, thereby to produce a second analog signal. 20. The apparatus in accordance with claim 11 further comprising: a decimator for filtering the sequence of elements ynto produce one element of a sequence D for each k successive elements ynwhere k is an integer greater than 1. 21. The apparatus in accordance with claim 20 wherein sequence D consists of every kth element Dnof a sequence where N1 and N2 are integers and f-N1through fN2are real numbers. 22. The apparatus in accordance with claim 21 wherein f-N1through fN2are sized such that the decimator has a low pass transfer function. 23. A sigma-delta data converter comprising: first means for generating a sequence of elements dnrepresenting magnitudes; second means for generating a sequence of elements ynin response to a sequence of elements bn,wherein each of elements ynrepresents a same magnitude as a corresponding one of elements bnbut with lower resolution; third means for generating a sequence of elements rnof magnitudes that are functions of a quantization error difference between magnitudes represented by corresponding pairs of elements bnand yn; and fourth means for generating the sequence of element bn,wherein each element bnrepresents a difference between magnitudes represented by a corresponding pair of elements dnand rn. 24. The sigma-delta data converter in accordance with claim 23 wherein the third means comprises: means for generating a sequence of elements fn,each representing a quantization error difference between magnitudes represented by a corresponding pair of elements bnand yn; and means for filtering the fnsequence to produce the rnsequence. 25. The sigma-delta data converter in accordance with claim 24 further comprising: fifth means for providing a sequence of elements cnin response to the sequence of elements yn,wherein corresponding pairs of elements cnand ynrepresent similar magnitudes; and sixth means for generating the sequence of elements dnin response to the sequences of elements cnand xn. 26. The sigma-delta data converter in accordance with claim 25 wherein the sixth means comprises: means for generating a sequence of elements an,wherein each element anrepresents a magnitude proportional to a difference between a corresponding pair of elements xnand cn; and means for filtering seque nce anital-to-analog converter for converting sequence yninto a first analog signal. 27. The sigma-delta data converter in accordance with claim 26 further comprising: a digital-to-analog converter for converting sequence yninto a first analog signal. 28. The sigma-delta data converter in accordance with claim 27 further comprising: a low pass filter for filtering the first analog signal, thereby to produce a second analog signal. 29. The sigma-delta data converter in accordance with claim 26 further comprising: a digital decimator for filtering sequence ynto produce a sequence D' of elements wherein each element of sequence D' corresponds to a separate set of k elements of sequence ynand represents a magnitude that is proportional to a sum of magnitudes proportional to a sum of magnitudes represented by the corresponding set of k elements of sequence yn,where k is an integer greater than 1. 30. The sigma-delta data converter in accordance with claim 29 further comprising: a digital low pass filter for filtering sequence D' to produce a sequence D. UP>-1 comparison unit and the negative output of the kth+1 comparison unit, such that when the output of the positive output of the kth-1 comparison unit is less than the output of the negative output of the kth+1 comparison unit, the replacement signal is a first digital value, and when the output of the positive output of the kth-1 comparison unit is greater than the output of the negative output of the kth+1 comparison unit, the replacement signal is a second digital value. 7. The method of claim 6 wherein the first digital value is a high logical value, and the second digital value is a low digital value.
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