초록 ▼

A flextensional transducer projector shell design is disclosed. The shell design has a shape formed so as to reduce the stress placed on the transduction driver as compared to other shell designs. The shell design includes first and second bulbous end portions, which can each be adapted to receive a

A flextensional transducer projector shell design is disclosed. The shell design has a shape formed so as to reduce the stress placed on the transduction driver as compared to other shell designs. The shell design includes first and second bulbous end portions, which can each be adapted to receive a respective end of a transduction driver. A middle portion of the shell design has both concave sections and convex sections, thereby defining a wave profile.

대표청구항 ▼

A flextensional transducer projector shell design is disclosed. The shell design has a shape formed so as to reduce the stress placed on the transduction driver as compared to other shell designs. The shell design includes first and second bulbous end portions, which can each be adapted to receive a

A flextensional transducer projector shell design is disclosed. The shell design has a shape formed so as to reduce the stress placed on the transduction driver as compared to other shell designs. The shell design includes first and second bulbous end portions, which can each be adapted to receive a respective end of a transduction driver. A middle portion of the shell design has both concave sections and convex sections, thereby defining a wave profile. ity in a second cell in the first memory; and changing a number orbits stored per cell on the fly. 20. The method of claim 19 wherein storing data at a second density in a second cell includes storing fewer bits per cell in one of said first or second cells. 21. A method comprising: storing data at a first density in a first cell in a first memory; storing data at a second density in a second cell in the first memory, including storing fewer bits per cell in one of said first or second cells; and storing data at levels which are spaced from one another in at least one of said first cell and said second cell in order to improve read fidelity. 22. The method of claim 21 including storing data in a cell including a plurality of levels and tilling less than all of said levels. 23. The method of claim 22 including storing data in regularly spaced levels within a cell while leaving intervening levels within the cell unoccupied by stored data. 24. An article comprising a medium storing instructions that enable a processor-based system to: store data at a first density in a first cell in a first memory; store data at a second density in a second cell in said first memory; and store instructions that enable the processor-based system to change a number of bits stored per cell on the fly. 25. The article of claim 24 further storing instructions that enable the processor-based system to store fewer bits per cell in one of said first or second cells. 26. An article comprising a medium storing instructions that enable a processor-based system to: store data at a first density in a first cell in a first memory; store data at a, second density in a second cell in said first memory; and store fewer bits per cell in one of said first or second cells; and store data at levels which are spaced from one another in said cell in order to improve read fidelity. 27. The article of claim 26 further storing instructions that enable the processor-based system to store data in a cell including a plurality of levels and fill less than all of said levels. 28. The article of claim 27 further storing instructions that enable the processor-based system to store data in regularly spaced levels within a cell while leaving intervening levels within the cell unoccupied by stored data. 29. A memory comprising: a memory array including a first and second cell; and a controller coupled to said array to store data in said array at a first density in the first cell and to store data at a second density in the second cell, wherein said controller changes a number of bits stored per cell on the fly. 30. The memory of claim 29 wherein said controller stores data at levels that are spaced from one another in said cell in order to improve read fidelity. 31. The memory of claim 30 wherein said controller stores data in a cell including a plurality of levels and fills less than all of the levels. 32. The memory of claim 29 wherein said memory is a flash memory. 33. The memory of claim 32 wherein said memory is a multi-level cell memory. 34. The memory of claim 29 wherein said controller stores fewer bits per cell in one or said first or second cells. 35. A memory comprising: a memory array including a first and second cell; and a controller coupled to said array to store data in said array at a first density in the first cell and to store data at a second density in the second cell and to store data in regularly spaced levels within a cell while leaving intervening levels within the cell unoccupied by stored data. 36. The memory of claim 35 wherein said memory is a flash memory. 37. The memory of claim 36 wherein said memory is a multi-level cell memory. 38. The memory of claim 35 wherein said controller stores fewer bits per cell in one or said first or second cells. 39. A method comprising: storing data at a first density in a first cell in a first memory array; storing data at a second density in a second cell in the first memory a