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System and method for providing forward progress and avoiding starvation and livelock in a multiprocessor computer system 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-013/36
  • G06F-013/00
  • G06F-012/00
출원번호 US-0652984 (2000-08-31)
발명자 / 주소
  • Duncan, Samuel H.
  • Ho, Steven
출원인 / 주소
  • Hewlett-Packard Development Company, L.P.
인용정보 피인용 횟수 : 23  인용 특허 : 9

초록

A system and method avoids "livelock" and "starvation" among two or more input/output (I/O) devices of a symmetrical multiprocessor (SMP) computer system competing for the same data. The SMP computer system includes a plurality of interconnected processors, one or more memories that are shared by th

대표청구항

A system and method avoids "livelock" and "starvation" among two or more input/output (I/O) devices of a symmetrical multiprocessor (SMP) computer system competing for the same data. The SMP computer system includes a plurality of interconnected processors, one or more memories that are shared by th

이 특허에 인용된 특허 (9)

  1. Solomon Gary A. (Hillsboro OR) MacWilliams Peter D. (Aloha OR) Hayek George R. (Cameron Park CA) Wade Nicholas D. (Cameron Park CA) Asghar Abid (Sacramento CA), Arbitration signaling mechanism to prevent deadlock guarantee access latency, and guarantee acquisition latency for an e.
  2. James B. Keller ; Dale Gulick ; Larry Hewitt ; Geoffrey Strongin, Circuit and method for selectively stalling interrupt requests initiated by devices coupled to a multiprocessor system.
  3. Chin Kenneth T. ; Johnson Jerome J. ; Jones Phillip M. ; Lester Robert A. ; Piccirillo Gary J. ; Stevens Jeffrey C. ; Coffee C. Kevin ; Collins Michael J. ; Larson John, Computer system employing memory controller and bridge interface permitting concurrent operation.
  4. Young Gene F. ; Stevens Roy M. ; James Larry C., Directory-based coherency system for maintaining coherency in a dual-ported memory system.
  5. VanDoren Stephen R. ; Sharma Madhumitra ; Steely Simon C., Employing multiple channels for deadlock avoidance in a cache coherency protocol.
  6. Normoyle Kevin B. ; Csoppenszky Michael A. ; Boddu Jaybharat ; Su Jui-Cheng ; Han Alex S. ; Cherabuddi Rajasekhar ; Tzeng Tzungren, Low-latency, high-throughput, integrated cache coherent I/O system for a single-chip processor.
  7. Kalkunte Ramsesh (Acton MA) Rege Satish (Groton MA) Edgar Ronald (Raymond NH), Method and apparatus for arbitrating conflicts by monitoring number of access requests per unit of time in multiport mem.
  8. Sharma Madhumitra, Multi-processor system for transferring data without incurring deadlock using hierarchical virtual channels.
  9. James David V., System and method for changing the states of directory-based caches and memories from read/write to read-only.

이 특허를 인용한 특허 (23)

  1. Gaither,Blaine D., Cache system with groups of lines and with coherency for both single lines and groups of lines.
  2. Seidman, David Isaiah, Calculating in-flight metrics for non-interruptible business transactions.
  3. Louzoun, Eliel; Ben-Shahar, Yifat, Communication between two embedded processors.
  4. Nakayama, Keishi; Uehara, Keitaro; Aoyagi, Takashi; Toya, Shinichiro, Computer system and bus assignment method.
  5. Nakayama, Keishi; Uehara, Keitaro; Aoyagi, Takashi; Toya, Shinichiro, Computer system and bus assignment method.
  6. Daly, Jr., George W.; Fields, Jr., James S.; Guthrie, Guy L.; Starke, William J.; Stuecheli, Jeffrey A., Data processing system and method that permit pipelining of I/O write operations and multiple operation scopes.
  7. Lais, Eric N.; Thurber, Steve, Determination of one or more partitionable endpoints affected by an I/O message.
  8. Lais, Eric N.; Thurber, Steve, Determination via an indexed structure of one or more partitionable endpoints affected by an I/O message.
  9. Foster, Andrew, Device interfacing.
  10. Jahnke,Steven R., Embedded symmetric multiprocessor system with arbitration control of access to shared resources.
  11. Lais, Eric N.; Thurber, Steve, Injection of I/O messages.
  12. Lais, Eric N.; Thurber, Steve, Injection of I/O messages.
  13. Lais, Eric N.; Nordstrom, Gregory M.; Thurber, Steve, Interrupt source controller with scalable state structures.
  14. Golander, Amit; Heymann, Omer; Levison, Nadav; Robinson, Eric F., Livelock prevention mechanism in a ring shaped interconnect utilizing round robin sampling.
  15. Sugahara, Hirohide; Miyoshi, Takashi; Horie, Takeshi; Larson, Jeffrey D., Method and apparatus for avoiding starvation in computer network.
  16. Duncan,Samuel H.; Huang,Wei Je; Edmondson,John H., Method and apparatus for providing peer-to-peer data transfer within a computing environment.
  17. Duncan,Samuel H.; Huang,Wei Je; Edmondson,John H., Method and apparatus for providing peer-to-peer data transfer within a computing environment.
  18. Genduso, Thomas Basilio; Harper, Richard Edwin, Method and system for improving input/output performance by proactively flushing and locking an entire page out of caches of a multiprocessor system.
  19. King,James E.; Mayhead,Martin P.; Garnett,Paul J., Multiprocessor systems.
  20. Duncan,Samuel Hammond; Huang,Wei Je; Kanekal,Radha, Peer-to-peer data transfer method and apparatus with request limits.
  21. Riocreux, Peter Andrew; Mathewson, Bruce James; Laycock, Christopher William; Grisenthwaite, Richard Roy, Synchronising activities of various components in a distributed system.
  22. Dickson,Christopher; Caliga,David; O'Connor,James; Poznanovic,Daniel, System and method for explicit communication of messages between processes running on different nodes in a clustered multiprocessor system.
  23. Vartti,Kelvin S.; Williams,James A.; Englin,Donald C., System and method for maintaining memory coherency within a multi-processor data processing system.
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